arch/arm/dts/k3-j721e-main.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for J721E SoC Family Main Domain peripherals
   4  *
   5  * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
   6  */
   7
   8 &cbass_main {
   9         msmc_ram: sram@70000000 {
  10                 compatible = "mmio-sram";
  11                 reg = <0x0 0x70000000 0x0 0x800000>;
  12                 #address-cells = <1>;
  13                 #size-cells = <1>;
  14                 ranges = <0x0 0x0 0x70000000 0x800000>;
  15
  16                 atf-sram@0 {
  17                         reg = <0x0 0x20000>;
  18                 };
  19         };
  20
  21         gic500: interrupt-controller@1800000 {
  22                 compatible = "arm,gic-v3";
  23                 #address-cells = <2>;
  24                 #size-cells = <2>;
  25                 ranges;
  26                 #interrupt-cells = <3>;
  27                 interrupt-controller;
  28                 reg = <0x00 0x01800000 0x00 0x10000>,   /* GICD */
  29                       <0x00 0x01900000 0x00 0x100000>;  /* GICR */
  30
  31                 /* vcpumntirq: virtual CPU interface maintenance interrupt */
  32                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  33
  34                 gic_its: gic-its@18200000 {
  35                         compatible = "arm,gic-v3-its";
  36                         reg = <0x00 0x01820000 0x00 0x10000>;
  37                         socionext,synquacer-pre-its = <0x1000000 0x400000>;
  38                         msi-controller;
  39                         #msi-cells = <1>;
  40                 };
  41         };
  42
  43         smmu0: smmu@36600000 {
  44                 compatible = "arm,smmu-v3";
  45                 reg = <0x0 0x36600000 0x0 0x100000>;
  46                 interrupt-parent = <&gic500>;
  47                 interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
  48                              <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>;
  49                 interrupt-names = "eventq", "gerror";
  50                 #iommu-cells = <1>;
  51         };
  52
  53         secure_proxy_main: mailbox@32c00000 {
  54                 compatible = "ti,am654-secure-proxy";
  55                 #mbox-cells = <1>;
  56                 reg-names = "target_data", "rt", "scfg";
  57                 reg = <0x00 0x32c00000 0x00 0x100000>,
  58                       <0x00 0x32400000 0x00 0x100000>,
  59                       <0x00 0x32800000 0x00 0x100000>;
  60                 interrupt-names = "rx_011";
  61                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  62         };
  63
  64         main_pmx0: pinmux@11c000 {
  65                 compatible = "pinctrl-single";
  66                 /* Proxy 0 addressing */
  67                 reg = <0x0 0x11c000 0x0 0x2b4>;
  68                 #pinctrl-cells = <1>;
  69                 pinctrl-single,register-width = <32>;
  70                 pinctrl-single,function-mask = <0xffffffff>;
  71         };
  72
  73         main_uart0: serial@2800000 {
  74                 compatible = "ti,j721e-uart", "ti,am654-uart";
  75                 reg = <0x00 0x02800000 0x00 0x100>;
  76                 reg-shift = <2>;
  77                 reg-io-width = <4>;
  78                 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
  79                 clock-frequency = <48000000>;
  80                 current-speed = <115200>;
  81                 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
  82                 clocks = <&k3_clks 146 0>;
  83                 clock-names = "fclk";
  84         };
  85
  86         main_uart1: serial@2810000 {
  87                 compatible = "ti,j721e-uart", "ti,am654-uart";
  88                 reg = <0x00 0x02810000 0x00 0x100>;
  89                 reg-shift = <2>;
  90                 reg-io-width = <4>;
  91                 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
  92                 clock-frequency = <48000000>;
  93                 current-speed = <115200>;
  94                 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
  95                 clocks = <&k3_clks 278 0>;
  96                 clock-names = "fclk";
  97         };
  98
  99         main_uart2: serial@2820000 {
 100                 compatible = "ti,j721e-uart", "ti,am654-uart";
 101                 reg = <0x00 0x02820000 0x00 0x100>;
 102                 reg-shift = <2>;
 103                 reg-io-width = <4>;
 104                 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
 105                 clock-frequency = <48000000>;
 106                 current-speed = <115200>;
 107                 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
 108                 clocks = <&k3_clks 279 0>;
 109                 clock-names = "fclk";
 110         };
 111
 112         main_uart3: serial@2830000 {
 113                 compatible = "ti,j721e-uart", "ti,am654-uart";
 114                 reg = <0x00 0x02830000 0x00 0x100>;
 115                 reg-shift = <2>;
 116                 reg-io-width = <4>;
 117                 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
 118                 clock-frequency = <48000000>;
 119                 current-speed = <115200>;
 120                 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
 121                 clocks = <&k3_clks 280 0>;
 122                 clock-names = "fclk";
 123         };
 124
 125         main_uart4: serial@2840000 {
 126                 compatible = "ti,j721e-uart", "ti,am654-uart";
 127                 reg = <0x00 0x02840000 0x00 0x100>;
 128                 reg-shift = <2>;
 129                 reg-io-width = <4>;
 130                 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
 131                 clock-frequency = <48000000>;
 132                 current-speed = <115200>;
 133                 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
 134                 clocks = <&k3_clks 281 0>;
 135                 clock-names = "fclk";
 136         };
 137
 138         main_uart5: serial@2850000 {
 139                 compatible = "ti,j721e-uart", "ti,am654-uart";
 140                 reg = <0x00 0x02850000 0x00 0x100>;
 141                 reg-shift = <2>;
 142                 reg-io-width = <4>;
 143                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
 144                 clock-frequency = <48000000>;
 145                 current-speed = <115200>;
 146                 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
 147                 clocks = <&k3_clks 282 0>;
 148                 clock-names = "fclk";
 149         };
 150
 151         main_uart6: serial@2860000 {
 152                 compatible = "ti,j721e-uart", "ti,am654-uart";
 153                 reg = <0x00 0x02860000 0x00 0x100>;
 154                 reg-shift = <2>;
 155                 reg-io-width = <4>;
 156                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
 157                 clock-frequency = <48000000>;
 158                 current-speed = <115200>;
 159                 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
 160                 clocks = <&k3_clks 283 0>;
 161                 clock-names = "fclk";
 162         };
 163
 164         main_uart7: serial@2870000 {
 165                 compatible = "ti,j721e-uart", "ti,am654-uart";
 166                 reg = <0x00 0x02870000 0x00 0x100>;
 167                 reg-shift = <2>;
 168                 reg-io-width = <4>;
 169                 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
 170                 clock-frequency = <48000000>;
 171                 current-speed = <115200>;
 172                 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
 173                 clocks = <&k3_clks 284 0>;
 174                 clock-names = "fclk";
 175         };
 176
 177         main_uart8: serial@2880000 {
 178                 compatible = "ti,j721e-uart", "ti,am654-uart";
 179                 reg = <0x00 0x02880000 0x00 0x100>;
 180                 reg-shift = <2>;
 181                 reg-io-width = <4>;
 182                 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
 183                 clock-frequency = <48000000>;
 184                 current-speed = <115200>;
 185                 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
 186                 clocks = <&k3_clks 285 0>;
 187                 clock-names = "fclk";
 188         };
 189
 190         main_uart9: serial@2890000 {
 191                 compatible = "ti,j721e-uart", "ti,am654-uart";
 192                 reg = <0x00 0x02890000 0x00 0x100>;
 193                 reg-shift = <2>;
 194                 reg-io-width = <4>;
 195                 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
 196                 clock-frequency = <48000000>;
 197                 current-speed = <115200>;
 198                 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
 199                 clocks = <&k3_clks 286 0>;
 200                 clock-names = "fclk";
 201         };
 202
 203         main_sdhci0: sdhci@4f80000 {
 204                 compatible = "ti,j721e-sdhci-8bit";
 205                 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
 206                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 207                 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
 208                 clock-names = "clk_xin", "clk_ahb";
 209                 clocks = <&k3_clks 91 1>, <&k3_clks 91 0>;
 210                 assigned-clocks = <&k3_clks 91 1>;
 211                 assigned-clock-parents = <&k3_clks 91 2>;
 212                 bus-width = <8>;
 213                 ti,otap-del-sel = <0x2>;
 214                 ti,trm-icp = <0x8>;
 215                 dma-coherent;
 216         };
 217
 218         main_sdhci1: sdhci@4fb0000 {
 219                 compatible = "ti,j721e-sdhci-4bit";
 220                 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
 221                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 222                 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
 223                 clock-names = "clk_xin", "clk_ahb";
 224                 clocks = <&k3_clks 92 0>, <&k3_clks 92 5>;
 225                 assigned-clocks = <&k3_clks 92 0>;
 226                 assigned-clock-parents = <&k3_clks 92 1>;
 227                 ti,otap-del-sel = <0x2>;
 228                 ti,trm-icp = <0x8>;
 229                 dma-coherent;
 230         };
 231 };