1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
6 #include <dt-bindings/pinctrl/k3.h>
7 #include <dt-bindings/dma/k3-udma.h>
8 #include <dt-bindings/net/ti-dp83867.h>
12 stdout-path = "serial2:115200n8";
16 serial2 = &main_uart0;
17 ethernet0 = &cpsw_port1;
24 main_pmx0: pinmux@11c000 {
25 compatible = "pinctrl-single";
26 reg = <0x0 0x11c000 0x0 0x2e4>;
28 pinctrl-single,register-width = <32>;
29 pinctrl-single,function-mask = <0xffffffff>;
32 main_pmx1: pinmux@11c2e8 {
33 compatible = "pinctrl-single";
34 reg = <0x0 0x11c2e8 0x0 0x24>;
36 pinctrl-single,register-width = <32>;
37 pinctrl-single,function-mask = <0xffffffff>;
40 sdhci0: sdhci@04F80000 {
41 compatible = "arasan,sdhci-5.1";
42 reg = <0x0 0x4F80000 0x0 0x1000>,
43 <0x0 0x4F90000 0x0 0x400>;
44 clocks = <&k3_clks 47 1>;
45 power-domains = <&k3_pds 47>;
46 max-frequency = <25000000>;
49 sdhci1: sdhci@04FA0000 {
50 compatible = "arasan,sdhci-5.1";
51 reg = <0x0 0x4FA0000 0x0 0x1000>,
52 <0x0 0x4FB0000 0x0 0x400>;
53 clocks = <&k3_clks 48 1>;
54 power-domains = <&k3_pds 48>;
55 max-frequency = <25000000>;
62 wkup_pmx0: pinmux@4301c000 {
63 compatible = "pinctrl-single";
64 reg = <0x0 0x4301c000 0x0 0x118>;
66 pinctrl-single,register-width = <32>;
67 pinctrl-single,function-mask = <0xffffffff>;
70 navss_mcu: navss-mcu {
71 compatible = "simple-bus";
76 ti,sci-dev-id = <119>;
78 mcu_ringacc: ringacc@2b800000 {
79 compatible = "ti,am654-navss-ringacc";
80 reg = <0x0 0x2b800000 0x0 0x400000>,
81 <0x0 0x2b000000 0x0 0x400000>,
82 <0x0 0x28590000 0x0 0x100>,
83 <0x0 0x2a500000 0x0 0x40000>;
84 reg-names = "rt", "fifos",
85 "proxy_gcfg", "proxy_target";
87 ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
88 ti,dma-ring-reset-quirk;
90 ti,sci-dev-id = <195>;
93 mcu_udmap: udmap@285c0000 {
94 compatible = "ti,k3-navss-udmap";
95 reg = <0x0 0x285c0000 0x0 0x100>,
96 <0x0 0x2a800000 0x0 0x40000>,
97 <0x0 0x2aa00000 0x0 0x40000>;
98 reg-names = "gcfg", "rchanrt", "tchanrt";
101 ti,ringacc = <&mcu_ringacc>;
102 ti,psil-base = <0x6000>;
105 ti,sci-dev-id = <194>;
107 ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
109 ti,sci-rm-range-rchan = <0x3>, /* RX_HCHAN */
111 ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */
116 mcu_conf: scm_conf@40f00000 {
117 compatible = "syscon";
118 reg = <0x0 0x40f00000 0x0 0x20000>;
121 mcu_cpsw: cpsw_nuss@046000000 {
122 compatible = "ti,am654-cpsw-nuss";
123 #address-cells = <2>;
125 reg = <0x0 0x46000000 0x0 0x200000>;
126 reg-names = "cpsw_nuss";
129 clocks = <&k3_clks 5 10>;
131 power-domains = <&k3_pds 5>;
132 ti,psil-base = <0x7000>;
134 dmas = <&mcu_udmap &mcu_cpsw 0 UDMA_DIR_TX>,
135 <&mcu_udmap &mcu_cpsw 1 UDMA_DIR_TX>,
136 <&mcu_udmap &mcu_cpsw 2 UDMA_DIR_TX>,
137 <&mcu_udmap &mcu_cpsw 3 UDMA_DIR_TX>,
138 <&mcu_udmap &mcu_cpsw 4 UDMA_DIR_TX>,
139 <&mcu_udmap &mcu_cpsw 5 UDMA_DIR_TX>,
140 <&mcu_udmap &mcu_cpsw 6 UDMA_DIR_TX>,
141 <&mcu_udmap &mcu_cpsw 7 UDMA_DIR_TX>,
142 <&mcu_udmap &mcu_cpsw 0 UDMA_DIR_RX>;
143 dma-names = "tx0", "tx1", "tx2", "tx3",
144 "tx4", "tx5", "tx6", "tx7",
148 #address-cells = <1>;
159 ti,syscon-efuse = <&mcu_conf 0x200>;
164 #address-cells = <1>;
166 bus_freq = <1000000>;
170 linux,udma-mode = <UDMA_PKT_MODE>;
171 statictr-type = <PSIL_STATIC_TR_NONE>;
177 linux,udma-mode = <UDMA_PKT_MODE>;
178 statictr-type = <PSIL_STATIC_TR_NONE>;
184 linux,udma-mode = <UDMA_PKT_MODE>;
185 statictr-type = <PSIL_STATIC_TR_NONE>;
191 linux,udma-mode = <UDMA_PKT_MODE>;
192 statictr-type = <PSIL_STATIC_TR_NONE>;
198 linux,udma-mode = <UDMA_PKT_MODE>;
199 statictr-type = <PSIL_STATIC_TR_NONE>;
205 linux,udma-mode = <UDMA_PKT_MODE>;
206 statictr-type = <PSIL_STATIC_TR_NONE>;
212 linux,udma-mode = <UDMA_PKT_MODE>;
213 statictr-type = <PSIL_STATIC_TR_NONE>;
219 linux,udma-mode = <UDMA_PKT_MODE>;
220 statictr-type = <PSIL_STATIC_TR_NONE>;
237 k3_sysreset: sysreset-controller {
238 compatible = "ti,sci-sysreset";
257 main_uart0_pins_default: main_uart0_pins_default {
258 pinctrl-single,pins = <
259 AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
260 AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
261 AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
262 AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
267 main_mmc0_pins_default: main_mmc0_pins_default {
268 pinctrl-single,pins = <
269 AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
270 AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
271 AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
272 AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
273 AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
274 AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
275 AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
276 AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
277 AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
278 AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
279 AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
284 main_mmc1_pins_default: main_mmc1_pins_default {
285 pinctrl-single,pins = <
286 AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
287 AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
288 AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
289 AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
290 AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
291 AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
292 AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
293 AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
305 mcu_cpsw_pins_default: mcu_cpsw_pins_default {
306 pinctrl-single,pins = <
307 AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
308 AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
309 AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
310 AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
311 AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
312 AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
313 AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
314 AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
315 AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
316 AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
317 AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
318 AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
322 mcu_mdio_pins_default: mcu_mdio1_pins_default {
323 pinctrl-single,pins = <
324 AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
325 AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
332 pinctrl-names = "default";
333 pinctrl-0 = <&main_uart0_pins_default>;
342 pinctrl-names = "default";
343 pinctrl-0 = <&main_mmc0_pins_default>;
349 pinctrl-names = "default";
350 pinctrl-0 = <&main_mmc1_pins_default>;
351 sdhci-caps-mask = <0x7 0x0>;
355 pinctrl-names = "default";
356 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
360 phy0: ethernet-phy@0 {
362 /* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
363 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
364 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
365 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
370 phy-mode = "rgmii-id";
371 phy-handle = <&phy0>;
375 reg = <0x0 0x46000000 0x0 0x200000>,
376 <0x0 0x40f00200 0x0 0x2>;
377 reg-names = "cpsw_nuss", "mac_efuse";
379 cpsw-phy-sel@40f04040 {
380 compatible = "ti,am654-cpsw-phy-sel";
381 reg= <0x0 0x40f04040 0x0 0x4>;
382 reg-names = "gmii-sel";