1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
6 #include <dt-bindings/pinctrl/k3.h>
7 #include <dt-bindings/dma/k3-udma.h>
8 #include <dt-bindings/net/ti-dp83867.h>
12 stdout-path = "serial2:115200n8";
16 serial2 = &main_uart0;
17 ethernet0 = &cpsw_port1;
24 sdhci1: sdhci@04FA0000 {
25 compatible = "ti,am654-sdhci-5.1";
26 reg = <0x0 0x4FA0000 0x0 0x1000>,
27 <0x0 0x4FB0000 0x0 0x400>;
28 clocks =<&k3_clks 48 0>, <&k3_clks 48 1>;
29 clock-names = "clk_ahb", "clk_xin";
30 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
31 max-frequency = <25000000>;
32 ti,otap-del-sel-legacy = <0x0>;
33 ti,otap-del-sel-mmc-hs = <0x0>;
34 ti,otap-del-sel-sd-hs = <0x0>;
35 ti,otap-del-sel-sdr12 = <0x0>;
36 ti,otap-del-sel-sdr25 = <0x0>;
37 ti,otap-del-sel-sdr50 = <0x8>;
38 ti,otap-del-sel-sdr104 = <0x7>;
39 ti,otap-del-sel-ddr50 = <0x4>;
40 ti,otap-del-sel-ddr52 = <0x4>;
41 ti,otap-del-sel-hs200 = <0x7>;
50 navss_mcu: navss-mcu {
51 compatible = "simple-bus";
56 ti,sci-dev-id = <119>;
58 mcu_ringacc: ringacc@2b800000 {
59 compatible = "ti,am654-navss-ringacc";
60 reg = <0x0 0x2b800000 0x0 0x400000>,
61 <0x0 0x2b000000 0x0 0x400000>,
62 <0x0 0x28590000 0x0 0x100>,
63 <0x0 0x2a500000 0x0 0x40000>;
64 reg-names = "rt", "fifos",
65 "proxy_gcfg", "proxy_target";
67 ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
68 ti,dma-ring-reset-quirk;
70 ti,sci-dev-id = <195>;
73 mcu_udmap: udmap@285c0000 {
74 compatible = "ti,k3-navss-udmap";
75 reg = <0x0 0x285c0000 0x0 0x100>,
76 <0x0 0x2a800000 0x0 0x40000>,
77 <0x0 0x2aa00000 0x0 0x40000>;
78 reg-names = "gcfg", "rchanrt", "tchanrt";
81 ti,ringacc = <&mcu_ringacc>;
82 ti,psil-base = <0x6000>;
85 ti,sci-dev-id = <194>;
87 ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
89 ti,sci-rm-range-rchan = <0x3>, /* RX_HCHAN */
91 ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */
96 mcu_conf: scm_conf@40f00000 {
97 compatible = "syscon";
98 reg = <0x0 0x40f00000 0x0 0x20000>;
101 mcu_cpsw: cpsw_nuss@046000000 {
102 compatible = "ti,am654-cpsw-nuss";
103 #address-cells = <2>;
105 reg = <0x0 0x46000000 0x0 0x200000>;
106 reg-names = "cpsw_nuss";
109 clocks = <&k3_clks 5 10>;
111 power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
112 ti,psil-base = <0x7000>;
114 dmas = <&mcu_udmap &mcu_cpsw 0 UDMA_DIR_TX>,
115 <&mcu_udmap &mcu_cpsw 1 UDMA_DIR_TX>,
116 <&mcu_udmap &mcu_cpsw 2 UDMA_DIR_TX>,
117 <&mcu_udmap &mcu_cpsw 3 UDMA_DIR_TX>,
118 <&mcu_udmap &mcu_cpsw 4 UDMA_DIR_TX>,
119 <&mcu_udmap &mcu_cpsw 5 UDMA_DIR_TX>,
120 <&mcu_udmap &mcu_cpsw 6 UDMA_DIR_TX>,
121 <&mcu_udmap &mcu_cpsw 7 UDMA_DIR_TX>,
122 <&mcu_udmap &mcu_cpsw 0 UDMA_DIR_RX>;
123 dma-names = "tx0", "tx1", "tx2", "tx3",
124 "tx4", "tx5", "tx6", "tx7",
128 #address-cells = <1>;
139 ti,syscon-efuse = <&mcu_conf 0x200>;
144 #address-cells = <1>;
146 bus_freq = <1000000>;
150 linux,udma-mode = <UDMA_PKT_MODE>;
151 statictr-type = <PSIL_STATIC_TR_NONE>;
157 linux,udma-mode = <UDMA_PKT_MODE>;
158 statictr-type = <PSIL_STATIC_TR_NONE>;
164 linux,udma-mode = <UDMA_PKT_MODE>;
165 statictr-type = <PSIL_STATIC_TR_NONE>;
171 linux,udma-mode = <UDMA_PKT_MODE>;
172 statictr-type = <PSIL_STATIC_TR_NONE>;
178 linux,udma-mode = <UDMA_PKT_MODE>;
179 statictr-type = <PSIL_STATIC_TR_NONE>;
185 linux,udma-mode = <UDMA_PKT_MODE>;
186 statictr-type = <PSIL_STATIC_TR_NONE>;
192 linux,udma-mode = <UDMA_PKT_MODE>;
193 statictr-type = <PSIL_STATIC_TR_NONE>;
199 linux,udma-mode = <UDMA_PKT_MODE>;
200 statictr-type = <PSIL_STATIC_TR_NONE>;
217 k3_sysreset: sysreset-controller {
218 compatible = "ti,sci-sysreset";
238 wkup_i2c0_pins_default {
245 main_uart0_pins_default: main_uart0_pins_default {
246 pinctrl-single,pins = <
247 AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
248 AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
249 AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
250 AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
255 main_mmc0_pins_default: main_mmc0_pins_default {
256 pinctrl-single,pins = <
257 AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
258 AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
259 AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
260 AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
261 AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
262 AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
263 AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
264 AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
265 AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
266 AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
267 AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
268 AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
273 main_mmc1_pins_default: main_mmc1_pins_default {
274 pinctrl-single,pins = <
275 AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
276 AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
277 AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
278 AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
279 AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
280 AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
281 AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
282 AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
294 mcu_cpsw_pins_default: mcu_cpsw_pins_default {
295 pinctrl-single,pins = <
296 AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
297 AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
298 AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
299 AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
300 AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
301 AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
302 AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
303 AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
304 AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
305 AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
306 AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
307 AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
311 mcu_mdio_pins_default: mcu_mdio1_pins_default {
312 pinctrl-single,pins = <
313 AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
314 AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
321 pinctrl-names = "default";
322 pinctrl-0 = <&main_uart0_pins_default>;
333 pinctrl-names = "default";
334 pinctrl-0 = <&main_mmc1_pins_default>;
335 sdhci-caps-mask = <0x7 0x0>;
336 ti,driver-strength-ohm = <50>;
340 pinctrl-names = "default";
341 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
345 phy0: ethernet-phy@0 {
347 /* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
348 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
349 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
354 phy-mode = "rgmii-rxid";
355 phy-handle = <&phy0>;
359 reg = <0x0 0x46000000 0x0 0x200000>,
360 <0x0 0x40f00200 0x0 0x2>;
361 reg-names = "cpsw_nuss", "mac_efuse";
363 cpsw-phy-sel@40f04040 {
364 compatible = "ti,am654-cpsw-phy-sel";
365 reg= <0x0 0x40f04040 0x0 0x4>;
366 reg-names = "gmii-sel";
375 dr_mode = "peripheral";