arch/arm/dts/k3-am654-base-board-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
   4  */
   5
   6 #include <dt-bindings/pinctrl/k3.h>
   7 #include <dt-bindings/dma/k3-udma.h>
   8 #include <dt-bindings/net/ti-dp83867.h>
   9
  10 / {
  11         chosen {
  12                 stdout-path = "serial2:115200n8";
  13         };
  14
  15         aliases {
  16                 serial2 = &main_uart0;
  17                 ethernet0 = &cpsw_port1;
  18         };
  19 };
  20
  21 &cbass_main{
  22         u-boot,dm-spl;
  23
  24         sdhci1: sdhci@04FA0000 {
  25                 compatible = "ti,am654-sdhci-5.1";
  26                 reg = <0x0 0x4FA0000 0x0 0x1000>,
  27                       <0x0 0x4FB0000 0x0 0x400>;
  28                 clocks =<&k3_clks 48 0>, <&k3_clks 48 1>;
  29                 clock-names = "clk_ahb", "clk_xin";
  30                 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
  31                 max-frequency = <25000000>;
  32                 ti,otap-del-sel-legacy = <0x0>;
  33                 ti,otap-del-sel-mmc-hs = <0x0>;
  34                 ti,otap-del-sel-sd-hs = <0x0>;
  35                 ti,otap-del-sel-sdr12 = <0x0>;
  36                 ti,otap-del-sel-sdr25 = <0x0>;
  37                 ti,otap-del-sel-sdr50 = <0x8>;
  38                 ti,otap-del-sel-sdr104 = <0x7>;
  39                 ti,otap-del-sel-ddr50 = <0x4>;
  40                 ti,otap-del-sel-ddr52 = <0x4>;
  41                 ti,otap-del-sel-hs200 = <0x7>;
  42                 ti,trm-icp = <0x8>;
  43         };
  44
  45 };
  46
  47 &cbass_mcu {
  48         u-boot,dm-spl;
  49
  50         navss_mcu: navss-mcu {
  51                 compatible = "simple-bus";
  52                 #address-cells = <2>;
  53                 #size-cells = <2>;
  54                 ranges;
  55                 u-boot,dm-spl;
  56
  57                 ti,sci-dev-id = <119>;
  58
  59                 mcu_ringacc: ringacc@2b800000 {
  60                         compatible = "ti,am654-navss-ringacc";
  61                         reg =   <0x0 0x2b800000 0x0 0x400000>,
  62                                 <0x0 0x2b000000 0x0 0x400000>,
  63                                 <0x0 0x28590000 0x0 0x100>,
  64                                 <0x0 0x2a500000 0x0 0x40000>;
  65                         reg-names = "rt", "fifos",
  66                                     "proxy_gcfg", "proxy_target";
  67                         ti,num-rings = <286>;
  68                         ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
  69                         ti,dma-ring-reset-quirk;
  70                         ti,sci = <&dmsc>;
  71                         ti,sci-dev-id = <195>;
  72                         u-boot,dm-spl;
  73                 };
  74
  75                 mcu_udmap: udmap@285c0000 {
  76                         compatible = "ti,k3-navss-udmap";
  77                         reg =   <0x0 0x285c0000 0x0 0x100>,
  78                                 <0x0 0x2a800000 0x0 0x40000>,
  79                                 <0x0 0x2aa00000 0x0 0x40000>;
  80                         reg-names = "gcfg", "rchanrt", "tchanrt";
  81                         #dma-cells = <3>;
  82
  83                         ti,ringacc = <&mcu_ringacc>;
  84                         ti,psil-base = <0x6000>;
  85
  86                         ti,sci = <&dmsc>;
  87                         ti,sci-dev-id = <194>;
  88
  89                         ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
  90                                                 <0x2>; /* TX_CHAN */
  91                         ti,sci-rm-range-rchan = <0x3>, /* RX_HCHAN */
  92                                                 <0x4>; /* RX_CHAN */
  93                         ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */
  94                         dma-coherent;
  95                         u-boot,dm-spl;
  96                 };
  97         };
  98
  99         mcu_conf: scm_conf@40f00000 {
 100                 compatible = "syscon";
 101                 reg = <0x0 0x40f00000 0x0 0x20000>;
 102         };
 103
 104         mcu_cpsw: cpsw_nuss@046000000 {
 105                 compatible = "ti,am654-cpsw-nuss";
 106                 #address-cells = <2>;
 107                 #size-cells = <2>;
 108                 reg = <0x0 0x46000000 0x0 0x200000>;
 109                 reg-names = "cpsw_nuss";
 110                 ranges;
 111                 dma-coherent;
 112                 clocks = <&k3_clks 5 10>;
 113                 clock-names = "fck";
 114                 power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
 115                 ti,psil-base = <0x7000>;
 116
 117                 dmas = <&mcu_udmap &mcu_cpsw 0 UDMA_DIR_TX>,
 118                        <&mcu_udmap &mcu_cpsw 1 UDMA_DIR_TX>,
 119                        <&mcu_udmap &mcu_cpsw 2 UDMA_DIR_TX>,
 120                        <&mcu_udmap &mcu_cpsw 3 UDMA_DIR_TX>,
 121                        <&mcu_udmap &mcu_cpsw 4 UDMA_DIR_TX>,
 122                        <&mcu_udmap &mcu_cpsw 5 UDMA_DIR_TX>,
 123                        <&mcu_udmap &mcu_cpsw 6 UDMA_DIR_TX>,
 124                        <&mcu_udmap &mcu_cpsw 7 UDMA_DIR_TX>,
 125                        <&mcu_udmap &mcu_cpsw 0 UDMA_DIR_RX>;
 126                 dma-names = "tx0", "tx1", "tx2", "tx3",
 127                             "tx4", "tx5", "tx6", "tx7",
 128                             "rx";
 129
 130                 ports {
 131                         #address-cells = <1>;
 132                         #size-cells = <0>;
 133                         host: host@0 {
 134                                 reg = <0>;
 135                                 ti,label = "host";
 136                         };
 137
 138                         cpsw_port1: port@1 {
 139                                 reg = <1>;
 140                                 ti,mac-only;
 141                                 ti,label = "port1";
 142                                 ti,syscon-efuse = <&mcu_conf 0x200>;
 143                         };
 144                 };
 145
 146                 davinci_mdio: mdio {
 147                         #address-cells = <1>;
 148                         #size-cells = <0>;
 149                         bus_freq = <1000000>;
 150                 };
 151
 152                 ti,psil-config0 {
 153                         linux,udma-mode = <UDMA_PKT_MODE>;
 154                         statictr-type = <PSIL_STATIC_TR_NONE>;
 155                         ti,needs-epib;
 156                         ti,psd-size = <16>;
 157                 };
 158
 159                 ti,psil-config1 {
 160                         linux,udma-mode = <UDMA_PKT_MODE>;
 161                         statictr-type = <PSIL_STATIC_TR_NONE>;
 162                         ti,needs-epib;
 163                         ti,psd-size = <16>;
 164                 };
 165
 166                 ti,psil-config2 {
 167                         linux,udma-mode = <UDMA_PKT_MODE>;
 168                         statictr-type = <PSIL_STATIC_TR_NONE>;
 169                         ti,needs-epib;
 170                         ti,psd-size = <16>;
 171                 };
 172
 173                 ti,psil-config3 {
 174                         linux,udma-mode = <UDMA_PKT_MODE>;
 175                         statictr-type = <PSIL_STATIC_TR_NONE>;
 176                         ti,needs-epib;
 177                         ti,psd-size = <16>;
 178                 };
 179
 180                 ti,psil-config4 {
 181                         linux,udma-mode = <UDMA_PKT_MODE>;
 182                         statictr-type = <PSIL_STATIC_TR_NONE>;
 183                         ti,needs-epib;
 184                         ti,psd-size = <16>;
 185                 };
 186
 187                 ti,psil-config5 {
 188                         linux,udma-mode = <UDMA_PKT_MODE>;
 189                         statictr-type = <PSIL_STATIC_TR_NONE>;
 190                         ti,needs-epib;
 191                         ti,psd-size = <16>;
 192                 };
 193
 194                 ti,psil-config6 {
 195                         linux,udma-mode = <UDMA_PKT_MODE>;
 196                         statictr-type = <PSIL_STATIC_TR_NONE>;
 197                         ti,needs-epib;
 198                         ti,psd-size = <16>;
 199                 };
 200
 201                 ti,psil-config7 {
 202                         linux,udma-mode = <UDMA_PKT_MODE>;
 203                         statictr-type = <PSIL_STATIC_TR_NONE>;
 204                         ti,needs-epib;
 205                         ti,psd-size = <16>;
 206                 };
 207         };
 208 };
 209
 210 &cbass_wakeup {
 211         u-boot,dm-spl;
 212 };
 213
 214 &secure_proxy_main {
 215         u-boot,dm-spl;
 216 };
 217
 218 &dmsc {
 219         u-boot,dm-spl;
 220         k3_sysreset: sysreset-controller {
 221                 compatible = "ti,sci-sysreset";
 222                 u-boot,dm-spl;
 223         };
 224 };
 225
 226 &k3_pds {
 227         u-boot,dm-spl;
 228 };
 229
 230 &k3_clks {
 231         u-boot,dm-spl;
 232 };
 233
 234 &k3_reset {
 235         u-boot,dm-spl;
 236 };
 237
 238 &wkup_pmx0 {
 239         u-boot,dm-spl;
 240
 241         wkup_i2c0_pins_default {
 242                 u-boot,dm-spl;
 243         };
 244 };
 245
 246 &main_pmx0 {
 247         u-boot,dm-spl;
 248         main_uart0_pins_default: main_uart0_pins_default {
 249                 pinctrl-single,pins = <
 250                         AM65X_IOPAD(0x01e4, PIN_INPUT, 0)       /* (AF11) UART0_RXD */
 251                         AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0)      /* (AE11) UART0_TXD */
 252                         AM65X_IOPAD(0x01ec, PIN_INPUT, 0)       /* (AG11) UART0_CTSn */
 253                         AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0)      /* (AD11) UART0_RTSn */
 254                 >;
 255                 u-boot,dm-spl;
 256         };
 257
 258         main_mmc0_pins_default: main_mmc0_pins_default {
 259                 pinctrl-single,pins = <
 260                         AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0)      /* (B25) MMC0_CLK */
 261                         AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0)        /* (B27) MMC0_CMD */
 262                         AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0)        /* (A26) MMC0_DAT0 */
 263                         AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0)        /* (E25) MMC0_DAT1 */
 264                         AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0)        /* (C26) MMC0_DAT2 */
 265                         AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0)        /* (A25) MMC0_DAT3 */
 266                         AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0)        /* (E24) MMC0_DAT4 */
 267                         AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0)        /* (A24) MMC0_DAT5 */
 268                         AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0)        /* (B26) MMC0_DAT6 */
 269                         AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0)        /* (D25) MMC0_DAT7 */
 270                         AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0)        /* (A23) MMC0_SDCD */
 271                         AM65X_IOPAD(0x01b0, PIN_INPUT, 0)               /* (C25) MMC0_DS */
 272                 >;
 273                 u-boot,dm-spl;
 274         };
 275
 276         main_mmc1_pins_default: main_mmc1_pins_default {
 277                 pinctrl-single,pins = <
 278                         AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0)      /* (C27) MMC1_CLK */
 279                         AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0)        /* (C28) MMC1_CMD */
 280                         AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0)        /* (D28) MMC1_DAT0 */
 281                         AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0)        /* (E27) MMC1_DAT1 */
 282                         AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0)        /* (D26) MMC1_DAT2 */
 283                         AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0)        /* (D27) MMC1_DAT3 */
 284                         AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0)        /* (B24) MMC1_SDCD */
 285                         AM65X_IOPAD(0x02e0, PIN_INPUT, 0)                       /* (C24) MMC1_SDWP */
 286                 >;
 287                 u-boot,dm-spl;
 288         };
 289
 290 };
 291
 292 &main_pmx1 {
 293         u-boot,dm-spl;
 294 };
 295
 296 &wkup_pmx0 {
 297         mcu_cpsw_pins_default: mcu_cpsw_pins_default {
 298                 pinctrl-single,pins = <
 299                         AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
 300                         AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
 301                         AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
 302                         AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
 303                         AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
 304                         AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
 305                         AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
 306                         AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
 307                         AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
 308                         AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
 309                         AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
 310                         AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
 311                 >;
 312         };
 313
 314         mcu_mdio_pins_default: mcu_mdio1_pins_default {
 315                 pinctrl-single,pins = <
 316                         AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
 317                         AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
 318                 >;
 319         };
 320
 321         mcu-fss0-ospi0-pins-default {
 322                 u-boot,dm-spl;
 323         };
 324 };
 325
 326 &main_uart0 {
 327         u-boot,dm-spl;
 328         pinctrl-names = "default";
 329         pinctrl-0 = <&main_uart0_pins_default>;
 330         status = "okay";
 331 };
 332
 333 &sdhci0 {
 334         u-boot,dm-spl;
 335 };
 336
 337 &sdhci1 {
 338         u-boot,dm-spl;
 339         status = "okay";
 340         pinctrl-names = "default";
 341         pinctrl-0 = <&main_mmc1_pins_default>;
 342         sdhci-caps-mask = <0x7 0x0>;
 343         ti,driver-strength-ohm = <50>;
 344 };
 345
 346 &mcu_cpsw {
 347         pinctrl-names = "default";
 348         pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
 349 };
 350
 351 &davinci_mdio {
 352         phy0: ethernet-phy@0 {
 353                 reg = <0>;
 354                 /* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
 355                 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 356                 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 357         };
 358 };
 359
 360 &cpsw_port1 {
 361         phy-mode = "rgmii-rxid";
 362         phy-handle = <&phy0>;
 363 };
 364
 365 &mcu_cpsw {
 366         reg = <0x0 0x46000000 0x0 0x200000>,
 367               <0x0 0x40f00200 0x0 0x2>;
 368         reg-names = "cpsw_nuss", "mac_efuse";
 369
 370         cpsw-phy-sel@40f04040 {
 371                 compatible = "ti,am654-cpsw-phy-sel";
 372                 reg= <0x0 0x40f04040 0x0 0x4>;
 373                 reg-names = "gmii-sel";
 374         };
 375 };
 376
 377 &wkup_i2c0 {
 378         u-boot,dm-spl;
 379 };
 380
 381 &usb1 {
 382         dr_mode = "peripheral";
 383 };
 384
 385 &fss {
 386         u-boot,dm-spl;
 387 };
 388
 389 &ospi0 {
 390         u-boot,dm-spl;
 391
 392          flash@0{
 393                 u-boot,dm-spl;
 394         };
 395 };