arch/arm/dts/k3-am654-base-board-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
   4  */
   5
   6 #include <dt-bindings/pinctrl/k3.h>
   7 #include <dt-bindings/dma/k3-udma.h>
   8 #include <dt-bindings/net/ti-dp83867.h>
   9
  10 / {
  11         chosen {
  12                 stdout-path = "serial2:115200n8";
  13         };
  14
  15         aliases {
  16                 serial2 = &main_uart0;
  17                 ethernet0 = &cpsw_port1;
  18         };
  19 };
  20
  21 &cbass_main{
  22         u-boot,dm-spl;
  23
  24         main_pmx1: pinmux@11c2e8 {
  25                 compatible = "pinctrl-single";
  26                 reg = <0x0 0x11c2e8 0x0 0x24>;
  27                 #pinctrl-cells = <1>;
  28                 pinctrl-single,register-width = <32>;
  29                 pinctrl-single,function-mask = <0xffffffff>;
  30         };
  31
  32         sdhci1: sdhci@04FA0000 {
  33                 compatible = "ti,am654-sdhci-5.1";
  34                 reg = <0x0 0x4FA0000 0x0 0x1000>,
  35                       <0x0 0x4FB0000 0x0 0x400>;
  36                 clocks = <&k3_clks 48 1>;
  37                 power-domains = <&k3_pds 48>;
  38                 max-frequency = <25000000>;
  39                 ti,otap-del-sel = <0x2>;
  40                 ti,trm-icp = <0x8>;
  41         };
  42
  43 };
  44
  45 &cbass_mcu {
  46         u-boot,dm-spl;
  47         wkup_pmx0: pinmux@4301c000 {
  48                 compatible = "pinctrl-single";
  49                 reg = <0x0 0x4301c000 0x0 0x118>;
  50                 #pinctrl-cells = <1>;
  51                 pinctrl-single,register-width = <32>;
  52                 pinctrl-single,function-mask = <0xffffffff>;
  53         };
  54
  55         navss_mcu: navss-mcu {
  56                 compatible = "simple-bus";
  57                 #address-cells = <2>;
  58                 #size-cells = <2>;
  59                 ranges;
  60
  61                 ti,sci-dev-id = <119>;
  62
  63                 mcu_ringacc: ringacc@2b800000 {
  64                         compatible = "ti,am654-navss-ringacc";
  65                         reg =   <0x0 0x2b800000 0x0 0x400000>,
  66                                 <0x0 0x2b000000 0x0 0x400000>,
  67                                 <0x0 0x28590000 0x0 0x100>,
  68                                 <0x0 0x2a500000 0x0 0x40000>;
  69                         reg-names = "rt", "fifos",
  70                                     "proxy_gcfg", "proxy_target";
  71                         ti,num-rings = <286>;
  72                         ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
  73                         ti,dma-ring-reset-quirk;
  74                         ti,sci = <&dmsc>;
  75                         ti,sci-dev-id = <195>;
  76                 };
  77
  78                 mcu_udmap: udmap@285c0000 {
  79                         compatible = "ti,k3-navss-udmap";
  80                         reg =   <0x0 0x285c0000 0x0 0x100>,
  81                                 <0x0 0x2a800000 0x0 0x40000>,
  82                                 <0x0 0x2aa00000 0x0 0x40000>;
  83                         reg-names = "gcfg", "rchanrt", "tchanrt";
  84                         #dma-cells = <3>;
  85
  86                         ti,ringacc = <&mcu_ringacc>;
  87                         ti,psil-base = <0x6000>;
  88
  89                         ti,sci = <&dmsc>;
  90                         ti,sci-dev-id = <194>;
  91
  92                         ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
  93                                                 <0x2>; /* TX_CHAN */
  94                         ti,sci-rm-range-rchan = <0x3>, /* RX_HCHAN */
  95                                                 <0x4>; /* RX_CHAN */
  96                         ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */
  97                         dma-coherent;
  98                 };
  99         };
 100
 101         mcu_conf: scm_conf@40f00000 {
 102                 compatible = "syscon";
 103                 reg = <0x0 0x40f00000 0x0 0x20000>;
 104         };
 105
 106         mcu_cpsw: cpsw_nuss@046000000 {
 107                 compatible = "ti,am654-cpsw-nuss";
 108                 #address-cells = <2>;
 109                 #size-cells = <2>;
 110                 reg = <0x0 0x46000000 0x0 0x200000>;
 111                 reg-names = "cpsw_nuss";
 112                 ranges;
 113                 dma-coherent;
 114                 clocks = <&k3_clks 5 10>;
 115                 clock-names = "fck";
 116                 power-domains = <&k3_pds 5>;
 117                 ti,psil-base = <0x7000>;
 118
 119                 dmas = <&mcu_udmap &mcu_cpsw 0 UDMA_DIR_TX>,
 120                        <&mcu_udmap &mcu_cpsw 1 UDMA_DIR_TX>,
 121                        <&mcu_udmap &mcu_cpsw 2 UDMA_DIR_TX>,
 122                        <&mcu_udmap &mcu_cpsw 3 UDMA_DIR_TX>,
 123                        <&mcu_udmap &mcu_cpsw 4 UDMA_DIR_TX>,
 124                        <&mcu_udmap &mcu_cpsw 5 UDMA_DIR_TX>,
 125                        <&mcu_udmap &mcu_cpsw 6 UDMA_DIR_TX>,
 126                        <&mcu_udmap &mcu_cpsw 7 UDMA_DIR_TX>,
 127                        <&mcu_udmap &mcu_cpsw 0 UDMA_DIR_RX>;
 128                 dma-names = "tx0", "tx1", "tx2", "tx3",
 129                             "tx4", "tx5", "tx6", "tx7",
 130                             "rx";
 131
 132                 ports {
 133                         #address-cells = <1>;
 134                         #size-cells = <0>;
 135                         host: host@0 {
 136                                 reg = <0>;
 137                                 ti,label = "host";
 138                         };
 139
 140                         cpsw_port1: port@1 {
 141                                 reg = <1>;
 142                                 ti,mac-only;
 143                                 ti,label = "port1";
 144                                 ti,syscon-efuse = <&mcu_conf 0x200>;
 145                         };
 146                 };
 147
 148                 davinci_mdio: mdio {
 149                         #address-cells = <1>;
 150                         #size-cells = <0>;
 151                         bus_freq = <1000000>;
 152                 };
 153
 154                 ti,psil-config0 {
 155                         linux,udma-mode = <UDMA_PKT_MODE>;
 156                         statictr-type = <PSIL_STATIC_TR_NONE>;
 157                         ti,needs-epib;
 158                         ti,psd-size = <16>;
 159                 };
 160
 161                 ti,psil-config1 {
 162                         linux,udma-mode = <UDMA_PKT_MODE>;
 163                         statictr-type = <PSIL_STATIC_TR_NONE>;
 164                         ti,needs-epib;
 165                         ti,psd-size = <16>;
 166                 };
 167
 168                 ti,psil-config2 {
 169                         linux,udma-mode = <UDMA_PKT_MODE>;
 170                         statictr-type = <PSIL_STATIC_TR_NONE>;
 171                         ti,needs-epib;
 172                         ti,psd-size = <16>;
 173                 };
 174
 175                 ti,psil-config3 {
 176                         linux,udma-mode = <UDMA_PKT_MODE>;
 177                         statictr-type = <PSIL_STATIC_TR_NONE>;
 178                         ti,needs-epib;
 179                         ti,psd-size = <16>;
 180                 };
 181
 182                 ti,psil-config4 {
 183                         linux,udma-mode = <UDMA_PKT_MODE>;
 184                         statictr-type = <PSIL_STATIC_TR_NONE>;
 185                         ti,needs-epib;
 186                         ti,psd-size = <16>;
 187                 };
 188
 189                 ti,psil-config5 {
 190                         linux,udma-mode = <UDMA_PKT_MODE>;
 191                         statictr-type = <PSIL_STATIC_TR_NONE>;
 192                         ti,needs-epib;
 193                         ti,psd-size = <16>;
 194                 };
 195
 196                 ti,psil-config6 {
 197                         linux,udma-mode = <UDMA_PKT_MODE>;
 198                         statictr-type = <PSIL_STATIC_TR_NONE>;
 199                         ti,needs-epib;
 200                         ti,psd-size = <16>;
 201                 };
 202
 203                 ti,psil-config7 {
 204                         linux,udma-mode = <UDMA_PKT_MODE>;
 205                         statictr-type = <PSIL_STATIC_TR_NONE>;
 206                         ti,needs-epib;
 207                         ti,psd-size = <16>;
 208                 };
 209         };
 210 };
 211
 212 &cbass_wakeup {
 213         u-boot,dm-spl;
 214 };
 215
 216 &secure_proxy_main {
 217         u-boot,dm-spl;
 218 };
 219
 220 &dmsc {
 221         u-boot,dm-spl;
 222         k3_sysreset: sysreset-controller {
 223                 compatible = "ti,sci-sysreset";
 224                 u-boot,dm-spl;
 225         };
 226 };
 227
 228 &k3_pds {
 229         u-boot,dm-spl;
 230 };
 231
 232 &k3_clks {
 233         u-boot,dm-spl;
 234 };
 235
 236 &k3_reset {
 237         u-boot,dm-spl;
 238 };
 239
 240 &main_pmx0 {
 241         u-boot,dm-spl;
 242         main_uart0_pins_default: main_uart0_pins_default {
 243                 pinctrl-single,pins = <
 244                         AM65X_IOPAD(0x01e4, PIN_INPUT, 0)       /* (AF11) UART0_RXD */
 245                         AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0)      /* (AE11) UART0_TXD */
 246                         AM65X_IOPAD(0x01ec, PIN_INPUT, 0)       /* (AG11) UART0_CTSn */
 247                         AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0)      /* (AD11) UART0_RTSn */
 248                 >;
 249                 u-boot,dm-spl;
 250         };
 251
 252         main_mmc0_pins_default: main_mmc0_pins_default {
 253                 pinctrl-single,pins = <
 254                         AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0)      /* (B25) MMC0_CLK */
 255                         AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0)        /* (B27) MMC0_CMD */
 256                         AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0)        /* (A26) MMC0_DAT0 */
 257                         AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0)        /* (E25) MMC0_DAT1 */
 258                         AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0)        /* (C26) MMC0_DAT2 */
 259                         AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0)        /* (A25) MMC0_DAT3 */
 260                         AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0)        /* (E24) MMC0_DAT4 */
 261                         AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0)        /* (A24) MMC0_DAT5 */
 262                         AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0)        /* (B26) MMC0_DAT6 */
 263                         AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0)        /* (D25) MMC0_DAT7 */
 264                         AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0)        /* (A23) MMC0_SDCD */
 265                         AM65X_IOPAD(0x01b0, PIN_INPUT, 0)               /* (C25) MMC0_DS */
 266                 >;
 267                 u-boot,dm-spl;
 268         };
 269
 270         main_mmc1_pins_default: main_mmc1_pins_default {
 271                 pinctrl-single,pins = <
 272                         AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0)      /* (C27) MMC1_CLK */
 273                         AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0)        /* (C28) MMC1_CMD */
 274                         AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0)        /* (D28) MMC1_DAT0 */
 275                         AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0)        /* (E27) MMC1_DAT1 */
 276                         AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0)        /* (D26) MMC1_DAT2 */
 277                         AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0)        /* (D27) MMC1_DAT3 */
 278                         AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0)        /* (B24) MMC1_SDCD */
 279                         AM65X_IOPAD(0x02e0, PIN_INPUT, 0)                       /* (C24) MMC1_SDWP */
 280                 >;
 281                 u-boot,dm-spl;
 282         };
 283
 284 };
 285
 286 &main_pmx1 {
 287         u-boot,dm-spl;
 288 };
 289
 290 &wkup_pmx0 {
 291         mcu_cpsw_pins_default: mcu_cpsw_pins_default {
 292                 pinctrl-single,pins = <
 293                         AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
 294                         AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
 295                         AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
 296                         AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
 297                         AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
 298                         AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
 299                         AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
 300                         AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
 301                         AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
 302                         AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
 303                         AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
 304                         AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
 305                 >;
 306         };
 307
 308         mcu_mdio_pins_default: mcu_mdio1_pins_default {
 309                 pinctrl-single,pins = <
 310                         AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
 311                         AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
 312                 >;
 313         };
 314 };
 315
 316 &main_uart0 {
 317         u-boot,dm-spl;
 318         pinctrl-names = "default";
 319         pinctrl-0 = <&main_uart0_pins_default>;
 320         status = "okay";
 321 };
 322
 323 &sdhci0 {
 324         u-boot,dm-spl;
 325 };
 326
 327 &sdhci1 {
 328         u-boot,dm-spl;
 329         status = "okay";
 330         pinctrl-names = "default";
 331         pinctrl-0 = <&main_mmc1_pins_default>;
 332         sdhci-caps-mask = <0x7 0x0>;
 333         ti,driver-strength-ohm = <50>;
 334 };
 335
 336 &mcu_cpsw {
 337         pinctrl-names = "default";
 338         pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
 339 };
 340
 341 &davinci_mdio {
 342         phy0: ethernet-phy@0 {
 343                 reg = <0>;
 344                 /* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
 345                 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 346                 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 347                 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 348         };
 349 };
 350
 351 &cpsw_port1 {
 352         phy-mode = "rgmii-id";
 353         phy-handle = <&phy0>;
 354 };
 355
 356 &mcu_cpsw {
 357         reg = <0x0 0x46000000 0x0 0x200000>,
 358               <0x0 0x40f00200 0x0 0x2>;
 359         reg-names = "cpsw_nuss", "mac_efuse";
 360
 361         cpsw-phy-sel@40f04040 {
 362                 compatible = "ti,am654-cpsw-phy-sel";
 363                 reg= <0x0 0x40f04040 0x0 0x4>;
 364                 reg-names = "gmii-sel";
 365         };
 366 };