arch/arm/dts/k3-am65.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for AM6 SoC Family
   4  *
   5  * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
   6  */
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/k3.h>
  12 #include <dt-bindings/soc/ti,sci_pm_domain.h>
  13
  14 / {
  15         model = "Texas Instruments K3 AM654 SoC";
  16         compatible = "ti,am654";
  17         interrupt-parent = <&gic500>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         aliases {
  22                 serial0 = &wkup_uart0;
  23                 serial1 = &mcu_uart0;
  24                 serial2 = &main_uart0;
  25                 serial3 = &main_uart1;
  26                 serial4 = &main_uart2;
  27                 i2c0 = &wkup_i2c0;
  28                 i2c1 = &mcu_i2c0;
  29                 i2c2 = &main_i2c0;
  30                 i2c3 = &main_i2c1;
  31                 i2c4 = &main_i2c2;
  32                 i2c5 = &main_i2c3;
  33                 spi0 = &ospi0;
  34                 spi1 = &ospi1;
  35         };
  36
  37         chosen { };
  38
  39         firmware {
  40                 optee {
  41                         compatible = "linaro,optee-tz";
  42                         method = "smc";
  43                 };
  44
  45                 psci: psci {
  46                         compatible = "arm,psci-1.0";
  47                         method = "smc";
  48                 };
  49         };
  50
  51         a53_timer0: timer-cl0-cpu0 {
  52                 compatible = "arm,armv8-timer";
  53                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
  54                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
  55                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
  56                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
  57         };
  58
  59         pmu: pmu {
  60                 compatible = "arm,armv8-pmuv3";
  61                 /* Recommendation from GIC500 TRM Table A.3 */
  62                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
  63         };
  64
  65         cbass_main: interconnect@100000 {
  66                 compatible = "simple-bus";
  67                 #address-cells = <2>;
  68                 #size-cells = <2>;
  69                 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
  70                          <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
  71                          <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
  72                          <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
  73                          <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
  74                          <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
  75                          /* MCUSS Range */
  76                          <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
  77                          <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
  78                          <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
  79                          <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
  80                          <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
  81                          <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
  82                          <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
  83                          <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
  84                          <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
  85                          <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>,
  86                          <0x00 0x70000000 0x00 0x70000000 0x00 0x200000>,
  87                          <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>,
  88                          <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>;
  89
  90                 cbass_mcu: interconnect@28380000 {
  91                         compatible = "simple-bus";
  92                         #address-cells = <2>;
  93                         #size-cells = <2>;
  94                         ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
  95                                  <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
  96                                  <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
  97                                  <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
  98                                  <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
  99                                  <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
 100                                  <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
 101                                  <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
 102                                  <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI space 1 */
 103                                  <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>, /*  FSS OSPI0 data region 1 */
 104                                  <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, /* FSS OSPI0 data region 3*/
 105                                  <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; /* FSS OSPI1 data region 3*/
 106
 107                         cbass_wakeup: interconnect@42040000 {
 108                                 compatible = "simple-bus";
 109                                 #address-cells = <1>;
 110                                 #size-cells = <1>;
 111                                 /* WKUP  Basic peripherals */
 112                                 ranges = <0x42040000 0x00 0x42040000 0x03ac2400>;
 113                         };
 114                 };
 115         };
 116 };
 117
 118 /* Now include the peripherals for each bus segments */
 119 #include "k3-am65-main.dtsi"
 120 #include "k3-am65-mcu.dtsi"
 121 #include "k3-am65-wakeup.dtsi"