1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
4 * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
7 #include "skeleton.dtsi"
8 #include "armv7-m.dtsi"
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/imxrt1050-clock.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/memory/imxrt-sdram.h>
30 compatible = "fsl,imx-osc", "fixed-clock";
32 clock-frequency = <24000000>;
41 compatible = "fsl,imxrt-semc";
42 reg = <0x402f0000 0x4000>;
43 clocks = <&clks IMXRT1050_CLK_SEMC>;
44 pinctrl-0 = <&pinctrl_semc>;
45 pinctrl-names = "default";
49 lpuart1: serial@40184000 {
50 compatible = "fsl,imxrt-lpuart";
51 reg = <0x40184000 0x4000>;
52 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
53 clocks = <&clks IMXRT1050_CLK_LPUART1>;
58 iomuxc: iomuxc@401f8000 {
59 compatible = "fsl,imxrt-iomuxc";
60 reg = <0x401f8000 0x4000>;
66 compatible = "fsl,imxrt1050-ccm";
67 reg = <0x400fc000 0x4000>;
68 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
69 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
73 usdhc1: usdhc@402c0000 {
75 compatible = "fsl,imxrt-usdhc";
76 reg = <0x402c0000 0x10000>;
77 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
78 clocks = <&clks IMXRT1050_CLK_USDHC1>;
81 fsl,tuning-start-tap = <20>;
86 gpio1: gpio@401b8000 {
88 compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
89 reg = <0x401b8000 0x4000>;
90 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
91 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
95 #interrupt-cells = <2>;
98 gpio2: gpio@401bc000 {
100 compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
101 reg = <0x401bc000 0x4000>;
102 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
106 interrupt-controller;
107 #interrupt-cells = <2>;
110 gpio3: gpio@401c0000 {
112 compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
113 reg = <0x401c0000 0x4000>;
114 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
115 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
118 interrupt-controller;
119 #interrupt-cells = <2>;
122 gpio4: gpio@401c4000 {
124 compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
125 reg = <0x401c4000 0x4000>;
126 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
127 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
130 interrupt-controller;
131 #interrupt-cells = <2>;
134 gpio5: gpio@400c0000 {
136 compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
137 reg = <0x400c0000 0x4000>;
138 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
139 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
142 interrupt-controller;
143 #interrupt-cells = <2>;