1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
4 * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
8 #include "imxrt1050.dtsi"
9 #include "imxrt1050-evk-u-boot.dtsi"
10 #include <dt-bindings/pinctrl/pins-imxrt1050.h>
13 model = "NXP IMXRT1050-evk board";
14 compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";
17 bootargs = "root=/dev/ram";
18 stdout-path = "serial0:115200n8";
22 reg = <0x80000000 0x2000000>;
26 &lpuart1 { /* console */
27 pinctrl-names = "default";
28 pinctrl-0 = <&pinctrl_lpuart1>;
34 * Memory configuration from sdram datasheet IS42S16160J-6BLI
36 fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
42 fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS
46 fsl,sdram-timing = /bits/ 8 <0x2
64 fsl,base-address = <0x80000000>;
65 fsl,memory-size = <MEM_SIZE_32M>;
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_lpuart1>;
74 pinctrl_lpuart1: lpuart1grp {
76 MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD
78 MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD
83 pinctrl_semc: semcgrp {
85 MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00
87 MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01
89 MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02
91 MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03
93 MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04
95 MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05
97 MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06
99 MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07
101 MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00
103 MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
105 MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01
107 MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02
109 MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03
111 MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04
113 MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05
115 MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06
117 MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07
119 MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08
121 MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09
123 MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11
125 MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12
127 MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0
129 MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1
131 MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10
133 MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS
135 MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS
137 MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK
139 MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE
141 MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE
143 MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0
145 MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08
147 MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09
149 MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10
151 MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11
153 MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12
155 MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13
157 MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14
159 MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15
161 MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01
163 MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS
164 (IMX_PAD_SION | 0xf1) /* SEMC_DQS */
168 pinctrl_usdhc0: usdhc0grp {
170 MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B
172 MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT
174 MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD
176 MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK
178 MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3
180 MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2
182 MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1
184 MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0
192 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
193 pinctrl-0 = <&pinctrl_usdhc0>;
194 pinctrl-1 = <&pinctrl_usdhc0>;
195 pinctrl-2 = <&pinctrl_usdhc0>;
196 pinctrl-3 = <&pinctrl_usdhc0>;
199 cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;