arch/arm/dts/imx8mp.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <dt-bindings/clock/imx8mp-clock.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/input/input.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10
  11 #include "imx8mp-pinfunc.h"
  12
  13 / {
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         aliases {
  19                 ethernet0 = &fec;
  20                 gpio0 = &gpio1;
  21                 gpio1 = &gpio2;
  22                 gpio2 = &gpio3;
  23                 gpio3 = &gpio4;
  24                 gpio4 = &gpio5;
  25                 mmc0 = &usdhc1;
  26                 mmc1 = &usdhc2;
  27                 mmc2 = &usdhc3;
  28                 serial0 = &uart1;
  29                 serial1 = &uart2;
  30                 serial2 = &uart3;
  31                 serial3 = &uart4;
  32         };
  33
  34         cpus {
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 A53_0: cpu@0 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a53";
  41                         reg = <0x0>;
  42                         clock-latency = <61036>;
  43                         clocks = <&clk IMX8MP_CLK_ARM>;
  44                         enable-method = "psci";
  45                         next-level-cache = <&A53_L2>;
  46                 };
  47
  48                 A53_1: cpu@1 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a53";
  51                         reg = <0x1>;
  52                         clock-latency = <61036>;
  53                         clocks = <&clk IMX8MP_CLK_ARM>;
  54                         enable-method = "psci";
  55                         next-level-cache = <&A53_L2>;
  56                 };
  57
  58                 A53_2: cpu@2 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a53";
  61                         reg = <0x2>;
  62                         clock-latency = <61036>;
  63                         clocks = <&clk IMX8MP_CLK_ARM>;
  64                         enable-method = "psci";
  65                         next-level-cache = <&A53_L2>;
  66                 };
  67
  68                 A53_3: cpu@3 {
  69                         device_type = "cpu";
  70                         compatible = "arm,cortex-a53";
  71                         reg = <0x3>;
  72                         clock-latency = <61036>;
  73                         clocks = <&clk IMX8MP_CLK_ARM>;
  74                         enable-method = "psci";
  75                         next-level-cache = <&A53_L2>;
  76                 };
  77
  78                 A53_L2: l2-cache0 {
  79                         compatible = "cache";
  80                 };
  81         };
  82
  83         osc_32k: clock-osc-32k {
  84                 compatible = "fixed-clock";
  85                 #clock-cells = <0>;
  86                 clock-frequency = <32768>;
  87                 clock-output-names = "osc_32k";
  88         };
  89
  90         osc_24m: clock-osc-24m {
  91                 compatible = "fixed-clock";
  92                 #clock-cells = <0>;
  93                 clock-frequency = <24000000>;
  94                 clock-output-names = "osc_24m";
  95         };
  96
  97         clk_ext1: clock-ext1 {
  98                 compatible = "fixed-clock";
  99                 #clock-cells = <0>;
 100                 clock-frequency = <133000000>;
 101                 clock-output-names = "clk_ext1";
 102         };
 103
 104         clk_ext2: clock-ext2 {
 105                 compatible = "fixed-clock";
 106                 #clock-cells = <0>;
 107                 clock-frequency = <133000000>;
 108                 clock-output-names = "clk_ext2";
 109         };
 110
 111         clk_ext3: clock-ext3 {
 112                 compatible = "fixed-clock";
 113                 #clock-cells = <0>;
 114                 clock-frequency = <133000000>;
 115                 clock-output-names = "clk_ext3";
 116         };
 117
 118         clk_ext4: clock-ext4 {
 119                 compatible = "fixed-clock";
 120                 #clock-cells = <0>;
 121                 clock-frequency= <133000000>;
 122                 clock-output-names = "clk_ext4";
 123         };
 124
 125         psci {
 126                 compatible = "arm,psci-1.0";
 127                 method = "smc";
 128         };
 129
 130         timer {
 131                 compatible = "arm,armv8-timer";
 132                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
 133                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
 134                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
 135                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
 136                 clock-frequency = <8000000>;
 137                 arm,no-tick-in-suspend;
 138         };
 139
 140         soc@0 {
 141                 compatible = "simple-bus";
 142                 #address-cells = <1>;
 143                 #size-cells = <1>;
 144                 ranges = <0x0 0x0 0x0 0x3e000000>;
 145
 146                 aips1: bus@30000000 {
 147                         compatible = "simple-bus";
 148                         reg = <0x30000000 0x400000>;
 149                         #address-cells = <1>;
 150                         #size-cells = <1>;
 151                         ranges;
 152
 153                         gpio1: gpio@30200000 {
 154                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 155                                 reg = <0x30200000 0x10000>;
 156                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 157                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 158                                 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>;
 159                                 gpio-controller;
 160                                 #gpio-cells = <2>;
 161                                 interrupt-controller;
 162                                 #interrupt-cells = <2>;
 163                                 gpio-ranges = <&iomuxc 0 5 30>;
 164                         };
 165
 166                         gpio2: gpio@30210000 {
 167                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 168                                 reg = <0x30210000 0x10000>;
 169                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 170                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 171                                 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>;
 172                                 gpio-controller;
 173                                 #gpio-cells = <2>;
 174                                 interrupt-controller;
 175                                 #interrupt-cells = <2>;
 176                                 gpio-ranges = <&iomuxc 0 35 21>;
 177                         };
 178
 179                         gpio3: gpio@30220000 {
 180                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 181                                 reg = <0x30220000 0x10000>;
 182                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 183                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 184                                 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>;
 185                                 gpio-controller;
 186                                 #gpio-cells = <2>;
 187                                 interrupt-controller;
 188                                 #interrupt-cells = <2>;
 189                                 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 0 144 4>;
 190                         };
 191
 192                         gpio4: gpio@30230000 {
 193                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 194                                 reg = <0x30230000 0x10000>;
 195                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 196                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 197                                 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>;
 198                                 gpio-controller;
 199                                 #gpio-cells = <2>;
 200                                 interrupt-controller;
 201                                 #interrupt-cells = <2>;
 202                                 gpio-ranges = <&iomuxc 0 82 32>;
 203                         };
 204
 205                         gpio5: gpio@30240000 {
 206                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 207                                 reg = <0x30240000 0x10000>;
 208                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 209                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 210                                 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>;
 211                                 gpio-controller;
 212                                 #gpio-cells = <2>;
 213                                 interrupt-controller;
 214                                 #interrupt-cells = <2>;
 215                                 gpio-ranges = <&iomuxc 0 114 30>;
 216                         };
 217
 218                         wdog1: watchdog@30280000 {
 219                                 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
 220                                 reg = <0x30280000 0x10000>;
 221                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 222                                 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
 223                                 status = "disabled";
 224                         };
 225
 226                         iomuxc: pinctrl@30330000 {
 227                                 compatible = "fsl,imx8mp-iomuxc";
 228                                 reg = <0x30330000 0x10000>;
 229                         };
 230
 231                         gpr: iomuxc-gpr@30340000 {
 232                                 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
 233                                 reg = <0x30340000 0x10000>;
 234                         };
 235
 236                         ocotp: ocotp-ctrl@30350000 {
 237                                 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
 238                                 reg = <0x30350000 0x10000>;
 239                                 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
 240                                 /* For nvmem subnodes */
 241                                 #address-cells = <1>;
 242                                 #size-cells = <1>;
 243
 244                                 cpu_speed_grade: speed-grade@10 {
 245                                         reg = <0x10 4>;
 246                                 };
 247                         };
 248
 249                         anatop: anatop@30360000 {
 250                                 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
 251                                              "syscon";
 252                                 reg = <0x30360000 0x10000>;
 253                         };
 254
 255                         snvs: snvs@30370000 {
 256                                 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
 257                                 reg = <0x30370000 0x10000>;
 258
 259                                 snvs_rtc: snvs-rtc-lp {
 260                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 261                                         regmap =<&snvs>;
 262                                         offset = <0x34>;
 263                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 264                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 265                                         clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
 266                                         clock-names = "snvs-rtc";
 267                                 };
 268
 269                                 snvs_pwrkey: snvs-powerkey {
 270                                         compatible = "fsl,sec-v4.0-pwrkey";
 271                                         regmap = <&snvs>;
 272                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 273                                         linux,keycode = <KEY_POWER>;
 274                                         wakeup-source;
 275                                         status = "disabled";
 276                                 };
 277                         };
 278
 279                         clk: clock-controller@30380000 {
 280                                 compatible = "fsl,imx8mp-ccm";
 281                                 reg = <0x30380000 0x10000>;
 282                                 #clock-cells = <1>;
 283                                 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
 284                                          <&clk_ext3>, <&clk_ext4>;
 285                                 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
 286                                               "clk_ext3", "clk_ext4";
 287                                 assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>,
 288                                                   <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>,
 289                                                   <&clk IMX8MP_AUDIO_PLL1>,
 290                                                   <&clk IMX8MP_AUDIO_PLL2>;
 291                         };
 292
 293                         src: src@30390000 {
 294                                 compatible = "fsl,imx8mp-src", "fsl,imx8mq-src", "syscon";
 295                                 reg = <0x30390000 0x10000>;
 296                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 297                                 #reset-cells = <1>;
 298                         };
 299                 };
 300
 301                 aips2: bus@30400000 {
 302                         compatible = "simple-bus";
 303                         reg = <0x30400000 0x400000>;
 304                         #address-cells = <1>;
 305                         #size-cells = <1>;
 306                         ranges;
 307
 308                         pwm1: pwm@30660000 {
 309                                 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
 310                                 reg = <0x30660000 0x10000>;
 311                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 312                                 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
 313                                          <&clk IMX8MP_CLK_PWM1_ROOT>;
 314                                 clock-names = "ipg", "per";
 315                                 #pwm-cells = <2>;
 316                                 status = "disabled";
 317                         };
 318
 319                         pwm2: pwm@30670000 {
 320                                 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
 321                                 reg = <0x30670000 0x10000>;
 322                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 323                                 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
 324                                          <&clk IMX8MP_CLK_PWM2_ROOT>;
 325                                 clock-names = "ipg", "per";
 326                                 #pwm-cells = <2>;
 327                                 status = "disabled";
 328                         };
 329
 330                         pwm3: pwm@30680000 {
 331                                 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
 332                                 reg = <0x30680000 0x10000>;
 333                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 334                                 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
 335                                          <&clk IMX8MP_CLK_PWM3_ROOT>;
 336                                 clock-names = "ipg", "per";
 337                                 #pwm-cells = <2>;
 338                                 status = "disabled";
 339                         };
 340
 341                         pwm4: pwm@30690000 {
 342                                 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
 343                                 reg = <0x30690000 0x10000>;
 344                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 345                                 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
 346                                          <&clk IMX8MP_CLK_PWM4_ROOT>;
 347                                 clock-names = "ipg", "per";
 348                                 #pwm-cells = <2>;
 349                                 status = "disabled";
 350                         };
 351                 };
 352
 353                 aips3: bus@30800000 {
 354                         compatible = "simple-bus";
 355                         reg = <0x30800000 0x400000>;
 356                         #address-cells = <1>;
 357                         #size-cells = <1>;
 358                         ranges;
 359
 360                         ecspi1: spi@30820000 {
 361                                 #address-cells = <1>;
 362                                 #size-cells = <0>;
 363                                 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
 364                                 reg = <0x30820000 0x10000>;
 365                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 366                                 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
 367                                          <&clk IMX8MP_CLK_ECSPI1_ROOT>;
 368                                 clock-names = "ipg", "per";
 369                                 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
 370                                 dma-names = "rx", "tx";
 371                                 status = "disabled";
 372                         };
 373
 374                         ecspi2: spi@30830000 {
 375                                 #address-cells = <1>;
 376                                 #size-cells = <0>;
 377                                 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
 378                                 reg = <0x30830000 0x10000>;
 379                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 380                                 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
 381                                          <&clk IMX8MP_CLK_ECSPI2_ROOT>;
 382                                 clock-names = "ipg", "per";
 383                                 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
 384                                 dma-names = "rx", "tx";
 385                                 status = "disabled";
 386                         };
 387
 388                         ecspi3: spi@30840000 {
 389                                 #address-cells = <1>;
 390                                 #size-cells = <0>;
 391                                 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
 392                                 reg = <0x30840000 0x10000>;
 393                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 394                                 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
 395                                          <&clk IMX8MP_CLK_ECSPI3_ROOT>;
 396                                 clock-names = "ipg", "per";
 397                                 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
 398                                 dma-names = "rx", "tx";
 399                                 status = "disabled";
 400                         };
 401
 402                         uart1: serial@30860000 {
 403                                 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
 404                                 reg = <0x30860000 0x10000>;
 405                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 406                                 clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
 407                                          <&clk IMX8MP_CLK_UART1_ROOT>;
 408                                 clock-names = "ipg", "per";
 409                                 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
 410                                 dma-names = "rx", "tx";
 411                                 status = "disabled";
 412                         };
 413
 414                         uart3: serial@30880000 {
 415                                 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
 416                                 reg = <0x30880000 0x10000>;
 417                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 418                                 clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
 419                                          <&clk IMX8MP_CLK_UART3_ROOT>;
 420                                 clock-names = "ipg", "per";
 421                                 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
 422                                 dma-names = "rx", "tx";
 423                                 status = "disabled";
 424                         };
 425
 426                         uart2: serial@30890000 {
 427                                 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
 428                                 reg = <0x30890000 0x10000>;
 429                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 430                                 clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
 431                                          <&clk IMX8MP_CLK_UART2_ROOT>;
 432                                 clock-names = "ipg", "per";
 433                                 status = "disabled";
 434                         };
 435
 436                         i2c1: i2c@30a20000 {
 437                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
 438                                 #address-cells = <1>;
 439                                 #size-cells = <0>;
 440                                 reg = <0x30a20000 0x10000>;
 441                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 442                                 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>;
 443                                 status = "disabled";
 444                         };
 445
 446                         i2c2: i2c@30a30000 {
 447                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
 448                                 #address-cells = <1>;
 449                                 #size-cells = <0>;
 450                                 reg = <0x30a30000 0x10000>;
 451                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 452                                 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>;
 453                                 status = "disabled";
 454                         };
 455
 456                         i2c3: i2c@30a40000 {
 457                                 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
 458                                 #address-cells = <1>;
 459                                 #size-cells = <0>;
 460                                 reg = <0x30a40000 0x10000>;
 461                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 462                                 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>;
 463                                 status = "disabled";
 464                         };
 465
 466                         i2c4: i2c@30a50000 {
 467                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
 468                                 #address-cells = <1>;
 469                                 #size-cells = <0>;
 470                                 reg = <0x30a50000 0x10000>;
 471                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 472                                 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>;
 473                                 status = "disabled";
 474                         };
 475
 476                         uart4: serial@30a60000 {
 477                                 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
 478                                 reg = <0x30a60000 0x10000>;
 479                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 480                                 clocks = <&clk IMX8MP_CLK_UART4_ROOT>,
 481                                          <&clk IMX8MP_CLK_UART4_ROOT>;
 482                                 clock-names = "ipg", "per";
 483                                 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
 484                                 dma-names = "rx", "tx";
 485                                 status = "disabled";
 486                         };
 487
 488                         i2c5: i2c@30ad0000 {
 489                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
 490                                 #address-cells = <1>;
 491                                 #size-cells = <0>;
 492                                 reg = <0x30ad0000 0x10000>;
 493                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 494                                 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>;
 495                                 status = "disabled";
 496                         };
 497
 498                         i2c6: i2c@30ae0000 {
 499                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
 500                                 #address-cells = <1>;
 501                                 #size-cells = <0>;
 502                                 reg = <0x30ae0000 0x10000>;
 503                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 504                                 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>;
 505                                 status = "disabled";
 506                         };
 507
 508                         usdhc1: mmc@30b40000 {
 509                                 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
 510                                 reg = <0x30b40000 0x10000>;
 511                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 512                                 clocks = <&clk IMX8MP_CLK_DUMMY>,
 513                                          <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
 514                                          <&clk IMX8MP_CLK_USDHC1_ROOT>;
 515                                 clock-names = "ipg", "ahb", "per";
 516                                 fsl,tuning-start-tap = <20>;
 517                                 fsl,tuning-step= <2>;
 518                                 bus-width = <4>;
 519                                 status = "disabled";
 520                         };
 521
 522                         usdhc2: mmc@30b50000 {
 523                                 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
 524                                 reg = <0x30b50000 0x10000>;
 525                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 526                                 clocks = <&clk IMX8MP_CLK_DUMMY>,
 527                                          <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
 528                                          <&clk IMX8MP_CLK_USDHC2_ROOT>;
 529                                 clock-names = "ipg", "ahb", "per";
 530                                 fsl,tuning-start-tap = <20>;
 531                                 fsl,tuning-step= <2>;
 532                                 bus-width = <4>;
 533                                 status = "disabled";
 534                         };
 535
 536                         usdhc3: mmc@30b60000 {
 537                                 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
 538                                 reg = <0x30b60000 0x10000>;
 539                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 540                                 clocks = <&clk IMX8MP_CLK_DUMMY>,
 541                                          <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
 542                                          <&clk IMX8MP_CLK_USDHC3_ROOT>;
 543                                 clock-names = "ipg", "ahb", "per";
 544                                 fsl,tuning-start-tap = <20>;
 545                                 fsl,tuning-step= <2>;
 546                                 bus-width = <4>;
 547                                 status = "disabled";
 548                         };
 549
 550                         sdma1: dma-controller@30bd0000 {
 551                                 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
 552                                 reg = <0x30bd0000 0x10000>;
 553                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 554                                 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
 555                                          <&clk IMX8MP_CLK_SDMA1_ROOT>;
 556                                 clock-names = "ipg", "ahb";
 557                                 #dma-cells = <3>;
 558                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
 559                         };
 560
 561                         fec: ethernet@30be0000 {
 562                                 compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
 563                                 reg = <0x30be0000 0x10000>;
 564                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 565                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 566                                              <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 567                                 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,
 568                                          <&clk IMX8MP_CLK_SIM_ENET_ROOT>,
 569                                          <&clk IMX8MP_CLK_ENET_TIMER>,
 570                                          <&clk IMX8MP_CLK_ENET_REF>,
 571                                          <&clk IMX8MP_CLK_ENET_PHY_REF>;
 572                                 clock-names = "ipg", "ahb", "ptp",
 573                                               "enet_clk_ref", "enet_out";
 574                                 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
 575                                                   <&clk IMX8MP_CLK_ENET_TIMER>,
 576                                                   <&clk IMX8MP_CLK_ENET_REF>,
 577                                                   <&clk IMX8MP_CLK_ENET_TIMER>;
 578                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
 579                                                          <&clk IMX8MP_SYS_PLL2_100M>,
 580                                                          <&clk IMX8MP_SYS_PLL2_125M>;
 581                                 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
 582                                 fsl,num-tx-queues = <3>;
 583                                 fsl,num-rx-queues = <3>;
 584                                 status = "disabled";
 585                         };
 586                 };
 587
 588                 gic: interrupt-controller@38800000 {
 589                         compatible = "arm,gic-v3";
 590                         reg = <0x38800000 0x10000>,
 591                               <0x38880000 0xc0000>;
 592                         #interrupt-cells = <3>;
 593                         interrupt-controller;
 594                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 595                         interrupt-parent = <&gic>;
 596                 };
 597         };
 598 };