arch/arm/dts/imx7d-pico.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 //
   3 // Copyright 2017 NXP
   4
   5 /dts-v1/;
   6
   7 #include "imx7d.dtsi"
   8
   9
  10 / {
  11         aliases {
  12                 mmc0 = &usdhc3;
  13         };
  14
  15         /* Will be filled by the bootloader */
  16         memory@80000000 {
  17                 device_type = "memory";
  18                 reg = <0x80000000 0>;
  19         };
  20
  21         reg_wlreg_on: regulator-wlreg_on {
  22                 compatible = "regulator-fixed";
  23                 pinctrl-names = "default";
  24                 pinctrl-0 = <&pinctrl_reg_wlreg_on>;
  25                 regulator-name = "wlreg_on";
  26                 regulator-min-microvolt = <3300000>;
  27                 regulator-max-microvolt = <3300000>;
  28                 gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
  29                 enable-active-high;
  30         };
  31
  32         reg_2p5v: regulator-2p5v {
  33                 compatible = "regulator-fixed";
  34                 regulator-name = "2P5V";
  35                 regulator-min-microvolt = <2500000>;
  36                 regulator-max-microvolt = <2500000>;
  37                 regulator-always-on;
  38         };
  39
  40         reg_3p3v: regulator-3p3v {
  41                 compatible = "regulator-fixed";
  42                 regulator-name = "3P3V";
  43                 regulator-min-microvolt = <3300000>;
  44                 regulator-max-microvolt = <3300000>;
  45                 regulator-always-on;
  46         };
  47
  48         reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
  49                 pinctrl-names = "default";
  50                 pinctrl-0 = <&pinctrl_usbotg1_pwr>;
  51                 compatible = "regulator-fixed";
  52                 regulator-name = "usb_otg1_vbus";
  53                 regulator-min-microvolt = <5000000>;
  54                 regulator-max-microvolt = <5000000>;
  55                 gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
  56         };
  57
  58         reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
  59                 compatible = "regulator-fixed";
  60                 regulator-name = "usb_otg2_vbus";
  61                 regulator-min-microvolt = <5000000>;
  62                 regulator-max-microvolt = <5000000>;
  63         };
  64
  65         reg_vref_1v8: regulator-vref-1v8 {
  66                 compatible = "regulator-fixed";
  67                 regulator-name = "vref-1v8";
  68                 regulator-min-microvolt = <1800000>;
  69                 regulator-max-microvolt = <1800000>;
  70         };
  71
  72         usdhc2_pwrseq: usdhc2_pwrseq {
  73                 compatible = "mmc-pwrseq-simple";
  74                 clocks = <&clks IMX7D_CLKO2_ROOT_DIV>;
  75                 clock-names = "ext_clock";
  76         };
  77 };
  78
  79 &clks {
  80         assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
  81                           <&clks IMX7D_CLKO2_ROOT_DIV>;
  82         assigned-clock-parents = <&clks IMX7D_CKIL>;
  83         assigned-clock-rates = <0>, <32768>;
  84 };
  85
  86 &ecspi3 {
  87         cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
  88         pinctrl-names = "default";
  89         pinctrl-0 = <&pinctrl_ecspi3>;
  90         status = "okay";
  91 };
  92
  93 &fec1 {
  94         pinctrl-names = "default";
  95         pinctrl-0 = <&pinctrl_enet1>;
  96         assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
  97                           <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
  98         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
  99         assigned-clock-rates = <0>, <100000000>;
 100         phy-mode = "rgmii";
 101         phy-handle = <&ethphy0>;
 102         fsl,magic-packet;
 103         phy-reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
 104         status = "okay";
 105
 106         mdio {
 107                 #address-cells = <1>;
 108                 #size-cells = <0>;
 109
 110                 ethphy0: ethernet-phy@1 {
 111                         compatible = "ethernet-phy-ieee802.3-c22";
 112                         reg = <1>;
 113                         status = "okay";
 114                 };
 115         };
 116 };
 117
 118 &flexcan1 {
 119         pinctrl-names = "default";
 120         pinctrl-0 = <&pinctrl_can1>;
 121         status = "okay";
 122 };
 123
 124 &flexcan2 {
 125         pinctrl-names = "default";
 126         pinctrl-0 = <&pinctrl_can2>;
 127         status = "okay";
 128 };
 129
 130 &i2c1 {
 131         clock-frequency = <100000>;
 132         pinctrl-names = "default";
 133         pinctrl-0 = <&pinctrl_i2c1>;
 134         status = "okay";
 135 };
 136
 137 &i2c2 {
 138         pinctrl-names = "default";
 139         pinctrl-0 = <&pinctrl_i2c2>;
 140         status = "okay";
 141 };
 142
 143 &i2c4 {
 144         pinctrl-names = "default";
 145         pinctrl-0 = <&pinctrl_i2c4>;
 146         status = "okay";
 147
 148         pmic: pfuze3000@8 {
 149                 compatible = "fsl,pfuze3000";
 150                 reg = <0x08>;
 151
 152                 regulators {
 153                         sw1a_reg: sw1a {
 154                                 regulator-min-microvolt = <700000>;
 155                                 regulator-max-microvolt = <3300000>;
 156                                 regulator-boot-on;
 157                                 regulator-always-on;
 158                                 regulator-ramp-delay = <6250>;
 159                         };
 160                         /* use sw1c_reg to align with pfuze100/pfuze200 */
 161                         sw1c_reg: sw1b {
 162                                 regulator-min-microvolt = <700000>;
 163                                 regulator-max-microvolt = <1475000>;
 164                                 regulator-boot-on;
 165                                 regulator-always-on;
 166                                 regulator-ramp-delay = <6250>;
 167                         };
 168
 169                         sw2_reg: sw2 {
 170                                 regulator-min-microvolt = <1800000>;
 171                                 regulator-max-microvolt = <1850000>;
 172                                 regulator-boot-on;
 173                                 regulator-always-on;
 174                         };
 175
 176                         sw3a_reg: sw3 {
 177                                 regulator-min-microvolt = <900000>;
 178                                 regulator-max-microvolt = <1650000>;
 179                                 regulator-boot-on;
 180                                 regulator-always-on;
 181                         };
 182
 183                         swbst_reg: swbst {
 184                                 regulator-min-microvolt = <5000000>;
 185                                 regulator-max-microvolt = <5150000>;
 186                         };
 187
 188                         snvs_reg: vsnvs {
 189                                 regulator-min-microvolt = <1000000>;
 190                                 regulator-max-microvolt = <3000000>;
 191                                 regulator-boot-on;
 192                                 regulator-always-on;
 193                         };
 194
 195                         vref_reg: vrefddr {
 196                                 regulator-boot-on;
 197                                 regulator-always-on;
 198                         };
 199
 200                         vgen1_reg: vldo1 {
 201                                 regulator-min-microvolt = <1800000>;
 202                                 regulator-max-microvolt = <3300000>;
 203                                 regulator-always-on;
 204                         };
 205
 206                         vgen2_reg: vldo2 {
 207                                 regulator-min-microvolt = <800000>;
 208                                 regulator-max-microvolt = <1550000>;
 209                         };
 210
 211                         vgen3_reg: vccsd {
 212                                 regulator-min-microvolt = <2850000>;
 213                                 regulator-max-microvolt = <3300000>;
 214                                 regulator-always-on;
 215                         };
 216
 217                         vgen4_reg: v33 {
 218                                 regulator-min-microvolt = <2850000>;
 219                                 regulator-max-microvolt = <3300000>;
 220                                 regulator-always-on;
 221                         };
 222
 223                         vgen5_reg: vldo3 {
 224                                 regulator-min-microvolt = <1800000>;
 225                                 regulator-max-microvolt = <3300000>;
 226                                 regulator-always-on;
 227                         };
 228
 229                         vgen6_reg: vldo4 {
 230                                 regulator-min-microvolt = <1800000>;
 231                                 regulator-max-microvolt = <3300000>;
 232                                 regulator-always-on;
 233                         };
 234                 };
 235         };
 236 };
 237
 238 &sai1 {
 239         pinctrl-names = "default";
 240         pinctrl-0 = <&pinctrl_sai1>;
 241         assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
 242                           <&clks IMX7D_SAI1_ROOT_CLK>;
 243         assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
 244         assigned-clock-rates = <0>, <24576000>;
 245         status = "okay";
 246 };
 247
 248
 249 &pwm1 {
 250         pinctrl-names = "default";
 251         pinctrl-0 = <&pinctrl_pwm1>;
 252         status = "okay";
 253 };
 254
 255 &pwm2 {
 256         pinctrl-names = "default";
 257         pinctrl-0 = <&pinctrl_pwm2>;
 258         status = "okay";
 259 };
 260
 261 &pwm3 {
 262         pinctrl-names = "default";
 263         pinctrl-0 = <&pinctrl_pwm3>;
 264         status = "okay";
 265 };
 266
 267 &pwm4 { /* Backlight */
 268         status = "okay";
 269 };
 270
 271 &uart5 {
 272         pinctrl-names = "default";
 273         pinctrl-0 = <&pinctrl_uart5>;
 274         assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
 275         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 276         status = "okay";
 277 };
 278
 279 &uart6 {
 280         pinctrl-names = "default";
 281         pinctrl-0 = <&pinctrl_uart6>;
 282         assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
 283         assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
 284         uart-has-rtscts;
 285         status = "okay";
 286 };
 287
 288 &uart7 { /* Bluetooth */
 289         pinctrl-names = "default";
 290         pinctrl-0 = <&pinctrl_uart7>;
 291         assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
 292         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 293         uart-has-rtscts;
 294         status = "okay";
 295 };
 296
 297 &usbotg1 {
 298         vbus-supply = <&reg_usb_otg1_vbus>;
 299         status = "okay";
 300 };
 301
 302 &usbotg2 {
 303         vbus-supply = <&reg_usb_otg2_vbus>;
 304         dr_mode = "host";
 305         status = "okay";
 306 };
 307
 308 &usdhc1 {
 309         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 310         pinctrl-0 = <&pinctrl_usdhc1>;
 311         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 312         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 313         cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 314         bus-width = <4>;
 315         tuning-step = <2>;
 316         vmmc-supply = <&reg_3p3v>;
 317         wakeup-source;
 318         no-1-8-v;
 319         keep-power-in-suspend;
 320         status = "okay";
 321 };
 322
 323 &usdhc2 { /* Wifi SDIO */
 324         pinctrl-names = "default";
 325         pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_wifi_clk>;
 326         no-1-8-v;
 327         non-removable;
 328         keep-power-in-suspend;
 329         wakeup-source;
 330         vmmc-supply = <&reg_wlreg_on>;
 331         mmc-pwrseq = <&usdhc2_pwrseq>;
 332         status = "okay";
 333 };
 334
 335 &usdhc3 {
 336         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 337         pinctrl-0 = <&pinctrl_usdhc3>;
 338         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 339         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 340         assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
 341         assigned-clock-rates = <400000000>;
 342         bus-width = <8>;
 343         no-1-8-v;
 344         fsl,tuning-step = <2>;
 345         non-removable;
 346         status = "okay";
 347 };
 348
 349 &wdog1 {
 350         pinctrl-names = "default";
 351         pinctrl-0 = <&pinctrl_wdog>;
 352         fsl,ext-reset-output;
 353         status = "okay";
 354 };
 355
 356 &iomuxc {
 357         pinctrl_ecspi3: ecspi3grp {
 358                 fsl,pins = <
 359                         MX7D_PAD_I2C1_SCL__ECSPI3_MISO          0x2
 360                         MX7D_PAD_I2C1_SDA__ECSPI3_MOSI          0x2
 361                         MX7D_PAD_I2C2_SCL__ECSPI3_SCLK          0x2
 362                         MX7D_PAD_I2C2_SDA__GPIO4_IO11           0x14
 363                 >;
 364         };
 365
 366         pinctrl_i2c1: i2c1grp {
 367                 fsl,pins = <
 368                         MX7D_PAD_UART1_TX_DATA__I2C1_SDA        0x4000007f
 369                         MX7D_PAD_UART1_RX_DATA__I2C1_SCL        0x4000007f
 370                 >;
 371         };
 372
 373         pinctrl_i2c2: i2c2grp {
 374                 fsl,pins = <
 375                         MX7D_PAD_UART2_TX_DATA__I2C2_SDA        0x4000007f
 376                         MX7D_PAD_UART2_RX_DATA__I2C2_SCL        0x4000007f
 377                 >;
 378         };
 379
 380         pinctrl_enet1: enet1grp {
 381                 fsl,pins = <
 382                         MX7D_PAD_SD2_CD_B__ENET1_MDIO                   0x3
 383                         MX7D_PAD_SD2_WP__ENET1_MDC                      0x3
 384                         MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC       0x1
 385                         MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0       0x1
 386                         MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1       0x1
 387                         MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2       0x1
 388                         MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3       0x1
 389                         MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
 390                         MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC       0x1
 391                         MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0       0x1
 392                         MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1       0x1
 393                         MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2       0x1
 394                         MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3       0x1
 395                         MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
 396                         MX7D_PAD_SD3_RESET_B__GPIO6_IO11                0x1  /* Ethernet reset */
 397                 >;
 398         };
 399
 400         pinctrl_can1: can1frp {
 401                 fsl,pins = <
 402                         MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX      0x59
 403                         MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX      0x59
 404                 >;
 405         };
 406
 407         pinctrl_can2: can2frp {
 408                 fsl,pins = <
 409                         MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX      0x59
 410                         MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX      0x59
 411                 >;
 412         };
 413
 414         pinctrl_i2c4: i2c4grp {
 415                 fsl,pins = <
 416                         MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA         0x4000007f
 417                         MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL         0x4000007f
 418                 >;
 419         };
 420
 421         pinctrl_pwm1: pwm1 {
 422                 fsl,pins = <
 423                         MX7D_PAD_GPIO1_IO08__PWM1_OUT   0x7f
 424                 >;
 425         };
 426
 427         pinctrl_pwm2: pwm2 {
 428                 fsl,pins = <
 429                         MX7D_PAD_GPIO1_IO09__PWM2_OUT   0x7f
 430                 >;
 431         };
 432
 433         pinctrl_pwm3: pwm3 {
 434                 fsl,pins = <
 435                         MX7D_PAD_GPIO1_IO10__PWM3_OUT   0x7f
 436                 >;
 437         };
 438
 439         pinctrl_reg_wlreg_on: regregongrp {
 440                 fsl,pins = <
 441                         MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16        0x59
 442                 >;
 443         };
 444
 445         pinctrl_sai1: sai1grp {
 446                 fsl,pins = <
 447                         MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK     0x1f
 448                         MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC        0x1f
 449                         MX7D_PAD_ENET1_COL__SAI1_TX_DATA0       0x30
 450                         MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0    0x1f
 451                 >;
 452         };
 453
 454         pinctrl_uart5: uart5grp {
 455                 fsl,pins = <
 456                         MX7D_PAD_I2C4_SDA__UART5_DCE_TX         0x79
 457                         MX7D_PAD_I2C4_SCL__UART5_DCE_RX         0x79
 458                 >;
 459         };
 460
 461         pinctrl_uart6: uart6grp {
 462                 fsl,pins = <
 463                         MX7D_PAD_EPDC_DATA08__UART6_DCE_RX      0x79
 464                         MX7D_PAD_EPDC_DATA09__UART6_DCE_TX      0x79
 465                         MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS     0x79
 466                         MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS     0x79
 467                 >;
 468         };
 469
 470         pinctrl_uart7: uart7grp {
 471                 fsl,pins = <
 472                         MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX      0x79
 473                         MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX      0x79
 474                         MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS      0x79
 475                         MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS     0x79
 476                 >;
 477         };
 478
 479         pinctrl_usbotg1_pwr: usbotg_pwr {
 480                 fsl,pins = <
 481                         MX7D_PAD_UART3_TX_DATA__GPIO4_IO5       0x14
 482                 >;
 483         };
 484
 485         pinctrl_usdhc1: usdhc1grp {
 486                 fsl,pins = <
 487                         MX7D_PAD_SD1_CMD__SD1_CMD               0x59
 488                         MX7D_PAD_SD1_CLK__SD1_CLK               0x19
 489                         MX7D_PAD_SD1_DATA0__SD1_DATA0           0x59
 490                         MX7D_PAD_SD1_DATA1__SD1_DATA1           0x59
 491                         MX7D_PAD_SD1_DATA2__SD1_DATA2           0x59
 492                         MX7D_PAD_SD1_DATA3__SD1_DATA3           0x59
 493                         MX7D_PAD_SD1_CD_B__GPIO5_IO0            0x15
 494                 >;
 495         };
 496
 497         pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
 498                 fsl,pins = <
 499                         MX7D_PAD_SD1_CMD__SD1_CMD               0x5a
 500                         MX7D_PAD_SD1_CLK__SD1_CLK               0x1a
 501                         MX7D_PAD_SD1_DATA0__SD1_DATA0           0x5a
 502                         MX7D_PAD_SD1_DATA1__SD1_DATA1           0x5a
 503                         MX7D_PAD_SD1_DATA2__SD1_DATA2           0x5a
 504                         MX7D_PAD_SD1_DATA3__SD1_DATA3           0x5a
 505                         MX7D_PAD_SD1_CD_B__GPIO5_IO0            0x15
 506                 >;
 507         };
 508
 509         pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
 510                 fsl,pins = <
 511                         MX7D_PAD_SD1_CMD__SD1_CMD               0x5b
 512                         MX7D_PAD_SD1_CLK__SD1_CLK               0x1b
 513                         MX7D_PAD_SD1_DATA0__SD1_DATA0           0x5b
 514                         MX7D_PAD_SD1_DATA1__SD1_DATA1           0x5b
 515                         MX7D_PAD_SD1_DATA2__SD1_DATA2           0x5b
 516                         MX7D_PAD_SD1_DATA3__SD1_DATA3           0x5b
 517                         MX7D_PAD_SD1_CD_B__GPIO5_IO0            0x15
 518                 >;
 519         };
 520
 521         pinctrl_usdhc2: usdhc2grp {
 522                 fsl,pins = <
 523                         MX7D_PAD_SD2_CMD__SD2_CMD               0x59
 524                         MX7D_PAD_SD2_CLK__SD2_CLK               0x19
 525                         MX7D_PAD_SD2_DATA0__SD2_DATA0           0x59
 526                         MX7D_PAD_SD2_DATA1__SD2_DATA1           0x59
 527                         MX7D_PAD_SD2_DATA2__SD2_DATA2           0x59
 528                         MX7D_PAD_SD2_DATA3__SD2_DATA3           0x59
 529                 >;
 530         };
 531
 532         pinctrl_usdhc3: usdhc3grp {
 533                 fsl,pins = <
 534                         MX7D_PAD_SD3_CMD__SD3_CMD               0x59
 535                         MX7D_PAD_SD3_CLK__SD3_CLK               0x19
 536                         MX7D_PAD_SD3_DATA0__SD3_DATA0           0x59
 537                         MX7D_PAD_SD3_DATA1__SD3_DATA1           0x59
 538                         MX7D_PAD_SD3_DATA2__SD3_DATA2           0x59
 539                         MX7D_PAD_SD3_DATA3__SD3_DATA3           0x59
 540                         MX7D_PAD_SD3_DATA4__SD3_DATA4           0x59
 541                         MX7D_PAD_SD3_DATA5__SD3_DATA5           0x59
 542                         MX7D_PAD_SD3_DATA6__SD3_DATA6           0x59
 543                         MX7D_PAD_SD3_DATA7__SD3_DATA7           0x59
 544                 >;
 545         };
 546
 547         pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
 548                 fsl,pins = <
 549                         MX7D_PAD_SD3_CMD__SD3_CMD               0x5a
 550                         MX7D_PAD_SD3_CLK__SD3_CLK               0x1a
 551                         MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5a
 552                         MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5a
 553                         MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5a
 554                         MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5a
 555                         MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5a
 556                         MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5a
 557                         MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5a
 558                         MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5a
 559                 >;
 560         };
 561
 562         pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
 563                 fsl,pins = <
 564                         MX7D_PAD_SD3_CMD__SD3_CMD               0x5b
 565                         MX7D_PAD_SD3_CLK__SD3_CLK               0x1b
 566                         MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5b
 567                         MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5b
 568                         MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5b
 569                         MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5b
 570                         MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5b
 571                         MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5b
 572                         MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5b
 573                         MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5b
 574                 >;
 575         };
 576 };
 577
 578 &iomuxc_lpsr {
 579         pinctrl_wifi_clk: wificlkgrp {
 580                 fsl,pins = <
 581                         MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2     0x7d
 582                 >;
 583         };
 584
 585         pinctrl_wdog: wdoggrp {
 586                 fsl,pins = <
 587                         MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B  0x74
 588                 >;
 589         };
 590 };