1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
15 /* Will be filled by the bootloader */
17 device_type = "memory";
21 reg_wlreg_on: regulator-wlreg_on {
22 compatible = "regulator-fixed";
23 pinctrl-names = "default";
24 pinctrl-0 = <&pinctrl_reg_wlreg_on>;
25 regulator-name = "wlreg_on";
26 regulator-min-microvolt = <3300000>;
27 regulator-max-microvolt = <3300000>;
28 gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
32 reg_2p5v: regulator-2p5v {
33 compatible = "regulator-fixed";
34 regulator-name = "2P5V";
35 regulator-min-microvolt = <2500000>;
36 regulator-max-microvolt = <2500000>;
40 reg_3p3v: regulator-3p3v {
41 compatible = "regulator-fixed";
42 regulator-name = "3P3V";
43 regulator-min-microvolt = <3300000>;
44 regulator-max-microvolt = <3300000>;
48 reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_usbotg1_pwr>;
51 compatible = "regulator-fixed";
52 regulator-name = "usb_otg1_vbus";
53 regulator-min-microvolt = <5000000>;
54 regulator-max-microvolt = <5000000>;
55 gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
58 reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
59 compatible = "regulator-fixed";
60 regulator-name = "usb_otg2_vbus";
61 regulator-min-microvolt = <5000000>;
62 regulator-max-microvolt = <5000000>;
65 reg_vref_1v8: regulator-vref-1v8 {
66 compatible = "regulator-fixed";
67 regulator-name = "vref-1v8";
68 regulator-min-microvolt = <1800000>;
69 regulator-max-microvolt = <1800000>;
72 usdhc2_pwrseq: usdhc2_pwrseq {
73 compatible = "mmc-pwrseq-simple";
74 clocks = <&clks IMX7D_CLKO2_ROOT_DIV>;
75 clock-names = "ext_clock";
80 assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
81 <&clks IMX7D_CLKO2_ROOT_DIV>;
82 assigned-clock-parents = <&clks IMX7D_CKIL>;
83 assigned-clock-rates = <0>, <32768>;
87 cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
88 pinctrl-names = "default";
89 pinctrl-0 = <&pinctrl_ecspi3>;
94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_enet1>;
96 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
97 <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
98 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
99 assigned-clock-rates = <0>, <100000000>;
101 phy-handle = <ðphy0>;
103 phy-reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
107 #address-cells = <1>;
110 ethphy0: ethernet-phy@1 {
111 compatible = "ethernet-phy-ieee802.3-c22";
119 pinctrl-names = "default";
120 pinctrl-0 = <&pinctrl_can1>;
125 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_can2>;
131 clock-frequency = <100000>;
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_i2c1>;
138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_i2c2>;
144 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_i2c4>;
149 compatible = "fsl,pfuze3000";
154 regulator-min-microvolt = <700000>;
155 regulator-max-microvolt = <3300000>;
158 regulator-ramp-delay = <6250>;
160 /* use sw1c_reg to align with pfuze100/pfuze200 */
162 regulator-min-microvolt = <700000>;
163 regulator-max-microvolt = <1475000>;
166 regulator-ramp-delay = <6250>;
170 regulator-min-microvolt = <1800000>;
171 regulator-max-microvolt = <1850000>;
177 regulator-min-microvolt = <900000>;
178 regulator-max-microvolt = <1650000>;
184 regulator-min-microvolt = <5000000>;
185 regulator-max-microvolt = <5150000>;
189 regulator-min-microvolt = <1000000>;
190 regulator-max-microvolt = <3000000>;
201 regulator-min-microvolt = <1800000>;
202 regulator-max-microvolt = <3300000>;
207 regulator-min-microvolt = <800000>;
208 regulator-max-microvolt = <1550000>;
212 regulator-min-microvolt = <2850000>;
213 regulator-max-microvolt = <3300000>;
218 regulator-min-microvolt = <2850000>;
219 regulator-max-microvolt = <3300000>;
224 regulator-min-microvolt = <1800000>;
225 regulator-max-microvolt = <3300000>;
230 regulator-min-microvolt = <1800000>;
231 regulator-max-microvolt = <3300000>;
239 pinctrl-names = "default";
240 pinctrl-0 = <&pinctrl_sai1>;
241 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
242 <&clks IMX7D_SAI1_ROOT_CLK>;
243 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
244 assigned-clock-rates = <0>, <24576000>;
250 pinctrl-names = "default";
251 pinctrl-0 = <&pinctrl_pwm1>;
256 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_pwm2>;
262 pinctrl-names = "default";
263 pinctrl-0 = <&pinctrl_pwm3>;
267 &pwm4 { /* Backlight */
272 pinctrl-names = "default";
273 pinctrl-0 = <&pinctrl_uart5>;
274 assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
275 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
280 pinctrl-names = "default";
281 pinctrl-0 = <&pinctrl_uart6>;
282 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
283 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
288 &uart7 { /* Bluetooth */
289 pinctrl-names = "default";
290 pinctrl-0 = <&pinctrl_uart7>;
291 assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
292 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
298 vbus-supply = <®_usb_otg1_vbus>;
303 vbus-supply = <®_usb_otg2_vbus>;
309 pinctrl-names = "default", "state_100mhz", "state_200mhz";
310 pinctrl-0 = <&pinctrl_usdhc1>;
311 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
312 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
313 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
316 vmmc-supply = <®_3p3v>;
319 keep-power-in-suspend;
323 &usdhc2 { /* Wifi SDIO */
324 pinctrl-names = "default";
325 pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_wifi_clk>;
328 keep-power-in-suspend;
330 vmmc-supply = <®_wlreg_on>;
331 mmc-pwrseq = <&usdhc2_pwrseq>;
336 pinctrl-names = "default", "state_100mhz", "state_200mhz";
337 pinctrl-0 = <&pinctrl_usdhc3>;
338 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
339 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
340 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
341 assigned-clock-rates = <400000000>;
344 fsl,tuning-step = <2>;
350 pinctrl-names = "default";
351 pinctrl-0 = <&pinctrl_wdog>;
352 fsl,ext-reset-output;
357 pinctrl_ecspi3: ecspi3grp {
359 MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2
360 MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x2
361 MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x2
362 MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14
366 pinctrl_i2c1: i2c1grp {
368 MX7D_PAD_UART1_TX_DATA__I2C1_SDA 0x4000007f
369 MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x4000007f
373 pinctrl_i2c2: i2c2grp {
375 MX7D_PAD_UART2_TX_DATA__I2C2_SDA 0x4000007f
376 MX7D_PAD_UART2_RX_DATA__I2C2_SCL 0x4000007f
380 pinctrl_enet1: enet1grp {
382 MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
383 MX7D_PAD_SD2_WP__ENET1_MDC 0x3
384 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
385 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
386 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
387 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
388 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
389 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
390 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
391 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
392 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
393 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
394 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
395 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
396 MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x1 /* Ethernet reset */
400 pinctrl_can1: can1frp {
402 MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX 0x59
403 MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX 0x59
407 pinctrl_can2: can2frp {
409 MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX 0x59
410 MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX 0x59
414 pinctrl_i2c4: i2c4grp {
416 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
417 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
423 MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x7f
429 MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7f
435 MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x7f
439 pinctrl_reg_wlreg_on: regregongrp {
441 MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x59
445 pinctrl_sai1: sai1grp {
447 MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
448 MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f
449 MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30
450 MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f
454 pinctrl_uart5: uart5grp {
456 MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x79
457 MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x79
461 pinctrl_uart6: uart6grp {
463 MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x79
464 MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x79
465 MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x79
466 MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x79
470 pinctrl_uart7: uart7grp {
472 MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX 0x79
473 MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX 0x79
474 MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS 0x79
475 MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS 0x79
479 pinctrl_usbotg1_pwr: usbotg_pwr {
481 MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x14
485 pinctrl_usdhc1: usdhc1grp {
487 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
488 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
489 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
490 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
491 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
492 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
493 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15
497 pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
499 MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
500 MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
501 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
502 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
503 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
504 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
505 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15
509 pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
511 MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
512 MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
513 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
514 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
515 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
516 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
517 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15
521 pinctrl_usdhc2: usdhc2grp {
523 MX7D_PAD_SD2_CMD__SD2_CMD 0x59
524 MX7D_PAD_SD2_CLK__SD2_CLK 0x19
525 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
526 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
527 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
528 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
532 pinctrl_usdhc3: usdhc3grp {
534 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
535 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
536 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
537 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
538 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
539 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
540 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
541 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
542 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
543 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
547 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
549 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
550 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
551 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
552 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
553 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
554 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
555 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
556 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
557 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
558 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
562 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
564 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
565 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
566 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
567 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
568 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
569 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
570 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
571 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
572 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
573 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
579 pinctrl_wifi_clk: wificlkgrp {
581 MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x7d
585 pinctrl_wdog: wdoggrp {
587 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74