1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
16 /* Will be filled by the bootloader */
18 device_type = "memory";
22 reg_wlreg_on: regulator-wlreg_on {
23 compatible = "regulator-fixed";
24 pinctrl-names = "default";
25 pinctrl-0 = <&pinctrl_reg_wlreg_on>;
26 regulator-name = "wlreg_on";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
29 gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
33 reg_2p5v: regulator-2p5v {
34 compatible = "regulator-fixed";
35 regulator-name = "2P5V";
36 regulator-min-microvolt = <2500000>;
37 regulator-max-microvolt = <2500000>;
41 reg_3p3v: regulator-3p3v {
42 compatible = "regulator-fixed";
43 regulator-name = "3P3V";
44 regulator-min-microvolt = <3300000>;
45 regulator-max-microvolt = <3300000>;
49 reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
50 pinctrl-names = "default";
51 pinctrl-0 = <&pinctrl_usbotg1_pwr>;
52 compatible = "regulator-fixed";
53 regulator-name = "usb_otg1_vbus";
54 regulator-min-microvolt = <5000000>;
55 regulator-max-microvolt = <5000000>;
56 gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
59 reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
60 compatible = "regulator-fixed";
61 regulator-name = "usb_otg2_vbus";
62 regulator-min-microvolt = <5000000>;
63 regulator-max-microvolt = <5000000>;
66 reg_vref_1v8: regulator-vref-1v8 {
67 compatible = "regulator-fixed";
68 regulator-name = "vref-1v8";
69 regulator-min-microvolt = <1800000>;
70 regulator-max-microvolt = <1800000>;
73 usdhc2_pwrseq: usdhc2_pwrseq {
74 compatible = "mmc-pwrseq-simple";
75 clocks = <&clks IMX7D_CLKO2_ROOT_DIV>;
76 clock-names = "ext_clock";
81 assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
82 <&clks IMX7D_CLKO2_ROOT_DIV>;
83 assigned-clock-parents = <&clks IMX7D_CKIL>;
84 assigned-clock-rates = <0>, <32768>;
88 cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_ecspi3>;
95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_enet1>;
97 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
98 <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
99 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
100 assigned-clock-rates = <0>, <100000000>;
102 phy-handle = <ðphy0>;
104 phy-reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
108 #address-cells = <1>;
111 ethphy0: ethernet-phy@1 {
112 compatible = "ethernet-phy-ieee802.3-c22";
120 pinctrl-names = "default";
121 pinctrl-0 = <&pinctrl_can1>;
126 pinctrl-names = "default";
127 pinctrl-0 = <&pinctrl_can2>;
132 clock-frequency = <100000>;
133 pinctrl-names = "default";
134 pinctrl-0 = <&pinctrl_i2c1>;
139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_i2c2>;
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_i2c4>;
150 compatible = "fsl,pfuze3000";
155 regulator-min-microvolt = <700000>;
156 regulator-max-microvolt = <3300000>;
159 regulator-ramp-delay = <6250>;
161 /* use sw1c_reg to align with pfuze100/pfuze200 */
163 regulator-min-microvolt = <700000>;
164 regulator-max-microvolt = <1475000>;
167 regulator-ramp-delay = <6250>;
171 regulator-min-microvolt = <1800000>;
172 regulator-max-microvolt = <1850000>;
178 regulator-min-microvolt = <900000>;
179 regulator-max-microvolt = <1650000>;
185 regulator-min-microvolt = <5000000>;
186 regulator-max-microvolt = <5150000>;
190 regulator-min-microvolt = <1000000>;
191 regulator-max-microvolt = <3000000>;
202 regulator-min-microvolt = <1800000>;
203 regulator-max-microvolt = <3300000>;
208 regulator-min-microvolt = <800000>;
209 regulator-max-microvolt = <1550000>;
213 regulator-min-microvolt = <2850000>;
214 regulator-max-microvolt = <3300000>;
219 regulator-min-microvolt = <2850000>;
220 regulator-max-microvolt = <3300000>;
225 regulator-min-microvolt = <1800000>;
226 regulator-max-microvolt = <3300000>;
231 regulator-min-microvolt = <1800000>;
232 regulator-max-microvolt = <3300000>;
240 pinctrl-names = "default";
241 pinctrl-0 = <&pinctrl_sai1>;
242 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
243 <&clks IMX7D_SAI1_ROOT_CLK>;
244 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
245 assigned-clock-rates = <0>, <24576000>;
251 pinctrl-names = "default";
252 pinctrl-0 = <&pinctrl_pwm1>;
257 pinctrl-names = "default";
258 pinctrl-0 = <&pinctrl_pwm2>;
263 pinctrl-names = "default";
264 pinctrl-0 = <&pinctrl_pwm3>;
268 &pwm4 { /* Backlight */
273 pinctrl-names = "default";
274 pinctrl-0 = <&pinctrl_uart5>;
275 assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
276 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
281 pinctrl-names = "default";
282 pinctrl-0 = <&pinctrl_uart6>;
283 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
284 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
289 &uart7 { /* Bluetooth */
290 pinctrl-names = "default";
291 pinctrl-0 = <&pinctrl_uart7>;
292 assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
293 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
299 vbus-supply = <®_usb_otg1_vbus>;
300 dr_mode = "peripheral";
305 vbus-supply = <®_usb_otg2_vbus>;
311 pinctrl-names = "default", "state_100mhz", "state_200mhz";
312 pinctrl-0 = <&pinctrl_usdhc1>;
313 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
314 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
315 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
318 vmmc-supply = <®_3p3v>;
321 keep-power-in-suspend;
325 &usdhc2 { /* Wifi SDIO */
326 pinctrl-names = "default";
327 pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_wifi_clk>;
330 keep-power-in-suspend;
332 vmmc-supply = <®_wlreg_on>;
333 mmc-pwrseq = <&usdhc2_pwrseq>;
338 pinctrl-names = "default", "state_100mhz", "state_200mhz";
339 pinctrl-0 = <&pinctrl_usdhc3>;
340 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
341 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
342 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
343 assigned-clock-rates = <400000000>;
346 fsl,tuning-step = <2>;
352 pinctrl-names = "default";
353 pinctrl-0 = <&pinctrl_wdog>;
354 fsl,ext-reset-output;
359 pinctrl_ecspi3: ecspi3grp {
361 MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2
362 MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x2
363 MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x2
364 MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14
368 pinctrl_i2c1: i2c1grp {
370 MX7D_PAD_UART1_TX_DATA__I2C1_SDA 0x4000007f
371 MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x4000007f
375 pinctrl_i2c2: i2c2grp {
377 MX7D_PAD_UART2_TX_DATA__I2C2_SDA 0x4000007f
378 MX7D_PAD_UART2_RX_DATA__I2C2_SCL 0x4000007f
382 pinctrl_enet1: enet1grp {
384 MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
385 MX7D_PAD_SD2_WP__ENET1_MDC 0x3
386 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
387 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
388 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
389 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
390 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
391 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
392 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
393 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
394 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
395 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
396 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
397 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
398 MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x1 /* Ethernet reset */
402 pinctrl_can1: can1frp {
404 MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX 0x59
405 MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX 0x59
409 pinctrl_can2: can2frp {
411 MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX 0x59
412 MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX 0x59
416 pinctrl_i2c4: i2c4grp {
418 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
419 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
425 MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x7f
431 MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7f
437 MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x7f
441 pinctrl_reg_wlreg_on: regregongrp {
443 MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x59
447 pinctrl_sai1: sai1grp {
449 MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
450 MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f
451 MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30
452 MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f
456 pinctrl_uart5: uart5grp {
458 MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x79
459 MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x79
463 pinctrl_uart6: uart6grp {
465 MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x79
466 MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x79
467 MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x79
468 MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x79
472 pinctrl_uart7: uart7grp {
474 MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX 0x79
475 MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX 0x79
476 MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS 0x79
477 MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS 0x79
481 pinctrl_usbotg1_pwr: usbotg_pwr {
483 MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x14
487 pinctrl_usdhc1: usdhc1grp {
489 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
490 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
491 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
492 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
493 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
494 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
495 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15
499 pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
501 MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
502 MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
503 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
504 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
505 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
506 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
507 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15
511 pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
513 MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
514 MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
515 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
516 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
517 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
518 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
519 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15
523 pinctrl_usdhc2: usdhc2grp {
525 MX7D_PAD_SD2_CMD__SD2_CMD 0x59
526 MX7D_PAD_SD2_CLK__SD2_CLK 0x19
527 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
528 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
529 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
530 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
534 pinctrl_usdhc3: usdhc3grp {
536 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
537 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
538 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
539 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
540 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
541 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
542 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
543 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
544 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
545 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
549 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
551 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
552 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
553 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
554 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
555 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
556 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
557 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
558 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
559 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
560 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
564 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
566 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
567 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
568 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
569 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
570 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
571 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
572 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
573 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
574 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
575 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
581 pinctrl_wifi_clk: wificlkgrp {
583 MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x7d
587 pinctrl_wdog: wdoggrp {
589 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74