1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "imx7d-pico-u-boot.dtsi"
11 /* Will be filled by the bootloader */
13 device_type = "memory";
17 reg_wlreg_on: regulator-wlreg_on {
18 compatible = "regulator-fixed";
19 pinctrl-names = "default";
20 pinctrl-0 = <&pinctrl_reg_wlreg_on>;
21 regulator-name = "wlreg_on";
22 regulator-min-microvolt = <3300000>;
23 regulator-max-microvolt = <3300000>;
24 gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
28 reg_2p5v: regulator-2p5v {
29 compatible = "regulator-fixed";
30 regulator-name = "2P5V";
31 regulator-min-microvolt = <2500000>;
32 regulator-max-microvolt = <2500000>;
36 reg_3p3v: regulator-3p3v {
37 compatible = "regulator-fixed";
38 regulator-name = "3P3V";
39 regulator-min-microvolt = <3300000>;
40 regulator-max-microvolt = <3300000>;
44 reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_usbotg1_pwr>;
47 compatible = "regulator-fixed";
48 regulator-name = "usb_otg1_vbus";
49 regulator-min-microvolt = <5000000>;
50 regulator-max-microvolt = <5000000>;
51 gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
54 reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
55 compatible = "regulator-fixed";
56 regulator-name = "usb_otg2_vbus";
57 regulator-min-microvolt = <5000000>;
58 regulator-max-microvolt = <5000000>;
61 reg_vref_1v8: regulator-vref-1v8 {
62 compatible = "regulator-fixed";
63 regulator-name = "vref-1v8";
64 regulator-min-microvolt = <1800000>;
65 regulator-max-microvolt = <1800000>;
68 usdhc2_pwrseq: usdhc2_pwrseq {
69 compatible = "mmc-pwrseq-simple";
70 clocks = <&clks IMX7D_CLKO2_ROOT_DIV>;
71 clock-names = "ext_clock";
76 assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
77 <&clks IMX7D_CLKO2_ROOT_DIV>;
78 assigned-clock-parents = <&clks IMX7D_CKIL>;
79 assigned-clock-rates = <0>, <32768>;
83 cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_ecspi3>;
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_enet1>;
92 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
93 <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
94 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
95 assigned-clock-rates = <0>, <100000000>;
96 phy-mode = "rgmii-id";
97 phy-handle = <ðphy0>;
99 phy-reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
103 #address-cells = <1>;
106 ethphy0: ethernet-phy@1 {
107 compatible = "ethernet-phy-ieee802.3-c22";
115 pinctrl-names = "default";
116 pinctrl-0 = <&pinctrl_can1>;
121 pinctrl-names = "default";
122 pinctrl-0 = <&pinctrl_can2>;
127 clock-frequency = <100000>;
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_i2c1>;
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_i2c2>;
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_i2c4>;
145 compatible = "fsl,pfuze3000";
150 regulator-min-microvolt = <700000>;
151 regulator-max-microvolt = <3300000>;
154 regulator-ramp-delay = <6250>;
156 /* use sw1c_reg to align with pfuze100/pfuze200 */
158 regulator-min-microvolt = <700000>;
159 regulator-max-microvolt = <1475000>;
162 regulator-ramp-delay = <6250>;
166 regulator-min-microvolt = <1800000>;
167 regulator-max-microvolt = <1850000>;
173 regulator-min-microvolt = <900000>;
174 regulator-max-microvolt = <1650000>;
180 regulator-min-microvolt = <5000000>;
181 regulator-max-microvolt = <5150000>;
185 regulator-min-microvolt = <1000000>;
186 regulator-max-microvolt = <3000000>;
197 regulator-min-microvolt = <1800000>;
198 regulator-max-microvolt = <3300000>;
203 regulator-min-microvolt = <800000>;
204 regulator-max-microvolt = <1550000>;
208 regulator-min-microvolt = <2850000>;
209 regulator-max-microvolt = <3300000>;
214 regulator-min-microvolt = <2850000>;
215 regulator-max-microvolt = <3300000>;
220 regulator-min-microvolt = <1800000>;
221 regulator-max-microvolt = <3300000>;
226 regulator-min-microvolt = <1800000>;
227 regulator-max-microvolt = <3300000>;
235 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_sai1>;
237 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
238 <&clks IMX7D_SAI1_ROOT_CLK>;
239 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
240 assigned-clock-rates = <0>, <24576000>;
246 pinctrl-names = "default";
247 pinctrl-0 = <&pinctrl_pwm1>;
252 pinctrl-names = "default";
253 pinctrl-0 = <&pinctrl_pwm2>;
258 pinctrl-names = "default";
259 pinctrl-0 = <&pinctrl_pwm3>;
263 &pwm4 { /* Backlight */
268 pinctrl-names = "default";
269 pinctrl-0 = <&pinctrl_uart5>;
270 assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
271 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
276 pinctrl-names = "default";
277 pinctrl-0 = <&pinctrl_uart6>;
278 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
279 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
284 &uart7 { /* Bluetooth */
285 pinctrl-names = "default";
286 pinctrl-0 = <&pinctrl_uart7>;
287 assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
288 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
294 vbus-supply = <®_usb_otg1_vbus>;
299 vbus-supply = <®_usb_otg2_vbus>;
305 pinctrl-names = "default", "state_100mhz", "state_200mhz";
306 pinctrl-0 = <&pinctrl_usdhc1>;
307 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
308 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
309 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
312 vmmc-supply = <®_3p3v>;
315 keep-power-in-suspend;
319 &usdhc2 { /* Wifi SDIO */
320 pinctrl-names = "default";
321 pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_wifi_clk>;
324 keep-power-in-suspend;
326 vmmc-supply = <®_wlreg_on>;
327 mmc-pwrseq = <&usdhc2_pwrseq>;
332 pinctrl-names = "default", "state_100mhz", "state_200mhz";
333 pinctrl-0 = <&pinctrl_usdhc3>;
334 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
335 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
336 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
337 assigned-clock-rates = <400000000>;
340 fsl,tuning-step = <2>;
346 pinctrl-names = "default";
347 pinctrl-0 = <&pinctrl_wdog>;
348 fsl,ext-reset-output;
353 pinctrl_ecspi3: ecspi3grp {
355 MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2
356 MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x2
357 MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x2
358 MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14
362 pinctrl_i2c1: i2c1grp {
364 MX7D_PAD_UART1_TX_DATA__I2C1_SDA 0x4000007f
365 MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x4000007f
369 pinctrl_i2c2: i2c2grp {
371 MX7D_PAD_UART2_TX_DATA__I2C2_SDA 0x4000007f
372 MX7D_PAD_UART2_RX_DATA__I2C2_SCL 0x4000007f
376 pinctrl_enet1: enet1grp {
378 MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
379 MX7D_PAD_SD2_WP__ENET1_MDC 0x3
380 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
381 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
382 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
383 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
384 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
385 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
386 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
387 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
388 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
389 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
390 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
391 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
392 MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x1 /* Ethernet reset */
396 pinctrl_can1: can1frp {
398 MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX 0x59
399 MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX 0x59
403 pinctrl_can2: can2frp {
405 MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX 0x59
406 MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX 0x59
410 pinctrl_i2c4: i2c4grp {
412 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
413 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
419 MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x7f
425 MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7f
431 MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x7f
435 pinctrl_reg_wlreg_on: regregongrp {
437 MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x59
441 pinctrl_sai1: sai1grp {
443 MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
444 MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f
445 MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30
446 MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f
450 pinctrl_uart5: uart5grp {
452 MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x79
453 MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x79
457 pinctrl_uart6: uart6grp {
459 MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x79
460 MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x79
461 MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x79
462 MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x79
466 pinctrl_uart7: uart7grp {
468 MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX 0x79
469 MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX 0x79
470 MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS 0x79
471 MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS 0x79
475 pinctrl_usbotg1_pwr: usbotg_pwr {
477 MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x14
481 pinctrl_usdhc1: usdhc1grp {
483 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
484 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
485 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
486 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
487 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
488 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
489 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15
493 pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
495 MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
496 MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
497 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
498 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
499 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
500 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
501 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15
505 pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
507 MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
508 MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
509 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
510 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
511 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
512 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
513 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15
517 pinctrl_usdhc2: usdhc2grp {
519 MX7D_PAD_SD2_CMD__SD2_CMD 0x59
520 MX7D_PAD_SD2_CLK__SD2_CLK 0x19
521 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
522 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
523 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
524 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
528 pinctrl_usdhc3: usdhc3grp {
530 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
531 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
532 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
533 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
534 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
535 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
536 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
537 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
538 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
539 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
543 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
545 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
546 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
547 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
548 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
549 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
550 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
551 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
552 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
553 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
554 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
558 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
560 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
561 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
562 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
563 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
564 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
565 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
566 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
567 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
568 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
569 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
575 pinctrl_wifi_clk: wificlkgrp {
577 MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x7d
581 pinctrl_wdog: wdoggrp {
583 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74