arch/arm/dts/imx7-colibri.dts

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * Copyright 2016 Toradex AG
   4  */
   5
   6 /dts-v1/;
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include "imx7d.dtsi"
   9
  10 / {
  11         model = "Toradex Colibri iMX7S/D";
  12         compatible = "toradex,imx7-colibri", "fsl,imx7";
  13
  14         chosen {
  15                 stdout-path = &uart1;
  16         };
  17 };
  18
  19 &gpmi {
  20         pinctrl-names = "default";
  21         pinctrl-0 = <&pinctrl_gpmi_nand>;
  22         fsl,use-minimum-ecc;
  23         nand-on-flash-bbt;
  24         nand-ecc-mode = "hw";
  25         status = "okay";
  26 };
  27
  28 &i2c1 {
  29         pinctrl-names = "default", "gpio";
  30         pinctrl-0 = <&pinctrl_i2c1>;
  31         pinctrl-1 = <&pinctrl_i2c1_gpio>;
  32         sda-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
  33         scl-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
  34         status = "okay";
  35
  36         rn5t567@33 {
  37                 compatible = "ricoh,rn5t567";
  38                 reg = <0x33>;
  39         };
  40 };
  41
  42 &i2c4 {
  43         pinctrl-names = "default", "gpio";
  44         pinctrl-0 = <&pinctrl_i2c4>;
  45         pinctrl-1 = <&pinctrl_i2c4_gpio>;
  46         sda-gpios = <&gpio7 9 GPIO_ACTIVE_LOW>;
  47         scl-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>;
  48         status = "okay";
  49 };
  50
  51 &uart1 {
  52         pinctrl-names = "default";
  53         pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
  54         uart-has-rtscts;
  55         fsl,dte-mode;
  56         status = "okay";
  57 };
  58
  59 &iomuxc {
  60         pinctrl_gpmi_nand: gpmi-nand-grp {
  61                 fsl,pins = <
  62                         MX7D_PAD_SD3_CLK__NAND_CLE              0x71
  63                         MX7D_PAD_SD3_CMD__NAND_ALE              0x71
  64                         MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B       0x71
  65                         MX7D_PAD_SAI1_TX_DATA__NAND_READY_B     0x74
  66                         MX7D_PAD_SD3_STROBE__NAND_RE_B          0x71
  67                         MX7D_PAD_SD3_RESET_B__NAND_WE_B         0x71
  68                         MX7D_PAD_SD3_DATA0__NAND_DATA00         0x71
  69                         MX7D_PAD_SD3_DATA1__NAND_DATA01         0x71
  70                         MX7D_PAD_SD3_DATA2__NAND_DATA02         0x71
  71                         MX7D_PAD_SD3_DATA3__NAND_DATA03         0x71
  72                         MX7D_PAD_SD3_DATA4__NAND_DATA04         0x71
  73                         MX7D_PAD_SD3_DATA5__NAND_DATA05         0x71
  74                         MX7D_PAD_SD3_DATA6__NAND_DATA06         0x71
  75                         MX7D_PAD_SD3_DATA7__NAND_DATA07         0x71
  76                 >;
  77         };
  78
  79         pinctrl_i2c4: i2c4-grp {
  80                 fsl,pins = <
  81                         MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA      0x4000007f
  82                         MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL      0x4000007f
  83                 >;
  84         };
  85
  86         pinctrl_i2c4_gpio: i2c4-gpio-grp {
  87                         fsl,pins = <
  88                         MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9     0x4000007f
  89                         MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8     0x4000007f
  90                 >;
  91         };
  92
  93         pinctrl_uart1: uart1-grp {
  94                 fsl,pins = <
  95                         MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX    0x79
  96                         MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX    0x79
  97                         MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS    0x79
  98                         MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS    0x79
  99                 >;
 100         };
 101
 102         pinctrl_uart1_ctrl1: uart1-ctrl1-grp {
 103                 fsl,pins = <
 104                         MX7D_PAD_SD2_DATA1__GPIO5_IO15          0x14 /* DCD */
 105                         MX7D_PAD_SD2_DATA0__GPIO5_IO14          0x14 /* DTR */
 106                 >;
 107         };
 108 };
 109
 110 &iomuxc_lpsr {
 111         pinctrl_i2c1: i2c1-grp {
 112                 fsl,pins = <
 113                         MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA      0x4000007f
 114                         MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL      0x4000007f
 115                 >;
 116         };
 117
 118         pinctrl_i2c1_gpio: i2c1-gpio-grp {
 119                 fsl,pins = <
 120                         MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5     0x4000007f
 121                         MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4     0x4000007f
 122                 >;
 123         };
 124 };