arm64: zynqmp: PM: Specify power domains for DP related nodes
[oweals/u-boot.git] / arch / arm / dts / imx6ull.dtsi
1 /*
2  * Copyright 2015-2016 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  */
8
9 #include <dt-bindings/clock/imx6ul-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "imx6ull-pinfunc.h"
13 #include "imx6ull-pinfunc-snvs.h"
14 #include "skeleton.dtsi"
15
16 / {
17         aliases {
18                 can0 = &flexcan1;
19                 can1 = &flexcan2;
20                 ethernet0 = &fec1;
21                 ethernet1 = &fec2;
22                 gpio0 = &gpio1;
23                 gpio1 = &gpio2;
24                 gpio2 = &gpio3;
25                 gpio3 = &gpio4;
26                 gpio4 = &gpio5;
27                 i2c0 = &i2c1;
28                 i2c1 = &i2c2;
29                 i2c2 = &i2c3;
30                 i2c3 = &i2c4;
31                 mmc0 = &usdhc1;
32                 mmc1 = &usdhc2;
33                 serial0 = &uart1;
34                 serial1 = &uart2;
35                 serial2 = &uart3;
36                 serial3 = &uart4;
37                 serial4 = &uart5;
38                 serial5 = &uart6;
39                 serial6 = &uart7;
40                 serial7 = &uart8;
41                 spi0 = &ecspi1;
42                 spi1 = &ecspi2;
43                 spi2 = &ecspi3;
44                 spi3 = &ecspi4;
45                 usbphy0 = &usbphy1;
46                 usbphy1 = &usbphy2;
47         };
48
49         cpus {
50                 #address-cells = <1>;
51                 #size-cells = <0>;
52
53                 cpu0: cpu@0 {
54                         compatible = "arm,cortex-a7";
55                         device_type = "cpu";
56                         reg = <0>;
57                         clock-latency = <61036>; /* two CLK32 periods */
58                         operating-points = <
59                                 /* kHz  uV */
60                                 528000  1175000
61                                 99000   950000
62                         >;
63                         fsl,soc-operating-points = <
64                                 /* KHz  uV */
65                                 528000  1175000
66                                 99000   1175000
67                         >;
68                         clocks = <&clks IMX6UL_CLK_ARM>,
69                                  <&clks IMX6UL_CLK_PLL2_BUS>,
70                                  <&clks IMX6UL_CLK_PLL2_PFD2>,
71                                  <&clks IMX6UL_CA7_SECONDARY_SEL>,
72                                  <&clks IMX6UL_CLK_STEP>,
73                                  <&clks IMX6UL_CLK_PLL1_SW>,
74                                  <&clks IMX6UL_CLK_PLL1_SYS>,
75                                  <&clks IMX6UL_PLL1_BYPASS>,
76                                  <&clks IMX6UL_CLK_PLL1>,
77                                  <&clks IMX6UL_PLL1_BYPASS_SRC>,
78                                  <&clks IMX6UL_CLK_OSC>;
79                         clock-names = "arm", "pll2_bus",  "pll2_pfd2_396m", "secondary_sel", "step",
80                                       "pll1_sw", "pll1_sys", "pll1_bypass", "pll1", "pll1_bypass_src", "osc";
81                 };
82         };
83
84         intc: interrupt-controller@00a01000 {
85                 compatible = "arm,cortex-a7-gic";
86                 #interrupt-cells = <3>;
87                 interrupt-controller;
88                 reg = <0x00a01000 0x1000>,
89                       <0x00a02000 0x100>;
90         };
91
92         clocks {
93                 #address-cells = <1>;
94                 #size-cells = <0>;
95
96                 ckil: clock@0 {
97                         compatible = "fixed-clock";
98                         reg = <0>;
99                         #clock-cells = <0>;
100                         clock-frequency = <32768>;
101                         clock-output-names = "ckil";
102                 };
103
104                 osc: clock@1 {
105                         compatible = "fixed-clock";
106                         reg = <1>;
107                         #clock-cells = <0>;
108                         clock-frequency = <24000000>;
109                         clock-output-names = "osc";
110                 };
111
112                 ipp_di0: clock@2 {
113                         compatible = "fixed-clock";
114                         reg = <2>;
115                         #clock-cells = <0>;
116                         clock-frequency = <0>;
117                         clock-output-names = "ipp_di0";
118                 };
119
120                 ipp_di1: clock@3 {
121                         compatible = "fixed-clock";
122                         reg = <3>;
123                         #clock-cells = <0>;
124                         clock-frequency = <0>;
125                         clock-output-names = "ipp_di1";
126                 };
127         };
128
129         soc {
130                 #address-cells = <1>;
131                 #size-cells = <1>;
132                 compatible = "simple-bus";
133                 interrupt-parent = <&gpc>;
134                 ranges;
135
136                 busfreq {
137                         compatible = "fsl,imx_busfreq";
138                         clocks = <&clks IMX6UL_CLK_PLL2_PFD2>, <&clks IMX6UL_CLK_PLL2_198M>,
139                                  <&clks IMX6UL_CLK_PLL2_BUS>, <&clks IMX6UL_CLK_ARM>,
140                                  <&clks IMX6UL_CLK_PLL3_USB_OTG>, <&clks IMX6UL_CLK_PERIPH>,
141                                  <&clks IMX6UL_CLK_PERIPH_PRE>, <&clks IMX6UL_CLK_PERIPH_CLK2>,
142                                  <&clks IMX6UL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6UL_CLK_OSC>,
143                                  <&clks IMX6UL_CLK_AHB>, <&clks IMX6UL_CLK_AXI>,
144                                  <&clks IMX6UL_CLK_PERIPH2>, <&clks IMX6UL_CLK_PERIPH2_PRE>,
145                                  <&clks IMX6UL_CLK_PERIPH2_CLK2>, <&clks IMX6UL_CLK_PERIPH2_CLK2_SEL>,
146                                  <&clks IMX6UL_CLK_STEP>, <&clks IMX6UL_CLK_MMDC_P0_FAST>, <&clks IMX6UL_PLL1_BYPASS_SRC>,
147                                  <&clks IMX6UL_PLL1_BYPASS>, <&clks IMX6UL_CLK_PLL1_SYS>, <&clks IMX6UL_CLK_PLL1_SW>,
148                                  <&clks IMX6UL_CLK_PLL1>;
149                         clock-names = "pll2_pfd2_396m", "pll2_198m", "pll2_bus", "arm", "pll3_usb_otg",
150                                       "periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc",
151                                       "ahb", "ocram", "periph2", "periph2_pre", "periph2_clk2", "periph2_clk2_sel",
152                                       "step", "mmdc", "pll1_bypass_src", "pll1_bypass", "pll1_sys", "pll1_sw", "pll1";
153                         fsl,max_ddr_freq = <400000000>;
154                 };
155
156                 pmu {
157                         compatible = "arm,cortex-a7-pmu";
158                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
159                         status = "disabled";
160                 };
161
162                 ocrams: sram@00900000 {
163                         compatible = "fsl,lpm-sram";
164                         reg = <0x00900000 0x4000>;
165                 };
166
167                 ocrams_ddr: sram@00904000 {
168                         compatible = "fsl,ddr-lpm-sram";
169                         reg = <0x00904000 0x1000>;
170                 };
171
172                 ocram: sram@00905000 {
173                         compatible = "mmio-sram";
174                         reg = <0x00905000 0x1B000>;
175                 };
176
177                 dma_apbh: dma-apbh@01804000 {
178                         compatible = "fsl,imx6ul-dma-apbh", "fsl,imx28-dma-apbh";
179                         reg = <0x01804000 0x2000>;
180                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
181                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
182                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
183                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
184                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
185                         #dma-cells = <1>;
186                         dma-channels = <4>;
187                         clocks = <&clks IMX6UL_CLK_APBHDMA>;
188                 };
189
190                 gpmi: gpmi-nand@01806000{
191                         compatible = "fsl,imx6ull-gpmi-nand", "fsl, imx6ul-gpmi-nand";
192                         #address-cells = <1>;
193                         #size-cells = <1>;
194                         reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
195                         reg-names = "gpmi-nand", "bch";
196                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
197                         interrupt-names = "bch";
198                         clocks = <&clks IMX6UL_CLK_GPMI_IO>,
199                                  <&clks IMX6UL_CLK_GPMI_APB>,
200                                  <&clks IMX6UL_CLK_GPMI_BCH>,
201                                  <&clks IMX6UL_CLK_GPMI_BCH_APB>,
202                                  <&clks IMX6UL_CLK_PER_BCH>;
203                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
204                                       "gpmi_bch_apb", "per1_bch";
205                         dmas = <&dma_apbh 0>;
206                         dma-names = "rx-tx";
207                         status = "disabled";
208                 };
209
210                 aips1: aips-bus@02000000 {
211                         compatible = "fsl,aips-bus", "simple-bus";
212                         #address-cells = <1>;
213                         #size-cells = <1>;
214                         reg = <0x02000000 0x100000>;
215                         ranges;
216
217                         spba-bus@02000000 {
218                                 compatible = "fsl,spba-bus", "simple-bus";
219                                 #address-cells = <1>;
220                                 #size-cells = <1>;
221                                 reg = <0x02000000 0x40000>;
222                                 ranges;
223
224                                 spdif: spdif@02004000 {
225                                         compatible = "fsl,imx6ul-spdif", "fsl,imx35-spdif";
226                                         reg = <0x02004000 0x4000>;
227                                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
228                                         dmas = <&sdma 41 18 0>,
229                                                <&sdma 42 18 0>;
230                                         dma-names = "rx", "tx";
231                                         clocks = <&clks IMX6UL_CLK_SPDIF_GCLK>,
232                                                  <&clks IMX6UL_CLK_OSC>,
233                                                  <&clks IMX6UL_CLK_SPDIF>,
234                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>,
235                                                  <&clks IMX6UL_CLK_IPG>,
236                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>,
237                                                  <&clks IMX6UL_CLK_SPBA>;
238                                         clock-names = "core", "rxtx0",
239                                                       "rxtx1", "rxtx2",
240                                                       "rxtx3", "rxtx4",
241                                                       "rxtx5", "rxtx6",
242                                                       "rxtx7", "dma";
243                                         status = "disabled";
244                                 };
245
246                                 ecspi1: ecspi@02008000 {
247                                         #address-cells = <1>;
248                                         #size-cells = <0>;
249                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
250                                         reg = <0x02008000 0x4000>;
251                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
252                                         clocks = <&clks IMX6UL_CLK_ECSPI1>,
253                                                  <&clks IMX6UL_CLK_ECSPI1>;
254                                         clock-names = "ipg", "per";
255                                         dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
256                                         dma-names = "rx", "tx";
257                                         status = "disabled";
258                                 };
259
260                                 ecspi2: ecspi@0200c000 {
261                                         #address-cells = <1>;
262                                         #size-cells = <0>;
263                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
264                                         reg = <0x0200c000 0x4000>;
265                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
266                                         clocks = <&clks IMX6UL_CLK_ECSPI2>,
267                                                  <&clks IMX6UL_CLK_ECSPI2>;
268                                         clock-names = "ipg", "per";
269                                         dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
270                                         dma-names = "rx", "tx";
271                                         status = "disabled";
272                                 };
273
274                                 ecspi3: ecspi@02010000 {
275                                         #address-cells = <1>;
276                                         #size-cells = <0>;
277                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
278                                         reg = <0x02010000 0x4000>;
279                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
280                                         clocks = <&clks IMX6UL_CLK_ECSPI3>,
281                                                  <&clks IMX6UL_CLK_ECSPI3>;
282                                         clock-names = "ipg", "per";
283                                         dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
284                                         dma-names = "rx", "tx";
285                                         status = "disabled";
286                                 };
287
288                                 ecspi4: ecspi@02014000 {
289                                         #address-cells = <1>;
290                                         #size-cells = <0>;
291                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
292                                         reg = <0x02014000 0x4000>;
293                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
294                                         clocks = <&clks IMX6UL_CLK_ECSPI4>,
295                                                  <&clks IMX6UL_CLK_ECSPI4>;
296                                         clock-names = "ipg", "per";
297                                         dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
298                                         dma-names = "rx", "tx";
299                                         status = "disabled";
300                                 };
301
302                                 uart7: serial@02018000 {
303                                         compatible = "fsl,imx6ul-uart",
304                                                      "fsl,imx6q-uart", "fsl,imx21-uart";
305                                         reg = <0x02018000 0x4000>;
306                                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
307                                         clocks = <&clks IMX6UL_CLK_UART7_IPG>,
308                                                  <&clks IMX6UL_CLK_UART7_SERIAL>;
309                                         clock-names = "ipg", "per";
310                                         dmas = <&sdma 43 4 0>, <&sdma 44 4 0>;
311                                         dma-names = "rx", "tx";
312                                         status = "disabled";
313                                 };
314
315                                 uart1: serial@02020000 {
316                                         compatible = "fsl,imx6ul-uart",
317                                                      "fsl,imx6q-uart", "fsl,imx21-uart";
318                                         reg = <0x02020000 0x4000>;
319                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
320                                         clocks = <&clks IMX6UL_CLK_UART1_IPG>,
321                                                  <&clks IMX6UL_CLK_UART1_SERIAL>;
322                                         clock-names = "ipg", "per";
323                                         status = "disabled";
324                                 };
325
326                                 esai: esai@02024000 {
327                                         compatible = "fsl,imx6ull-esai";
328                                         reg = <0x02024000 0x4000>;
329                                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
330                                         clocks = <&clks IMX6UL_CLK_ESAI_IPG>,
331                                                  <&clks IMX6UL_CLK_ESAI_MEM>,
332                                                  <&clks IMX6UL_CLK_ESAI_EXTAL>,
333                                                  <&clks IMX6UL_CLK_ESAI_IPG>,
334                                                  <&clks IMX6UL_CLK_SPBA>;
335                                         clock-names = "core", "mem", "extal",
336                                                       "fsys", "dma";
337                                         dmas = <&sdma 0 21 0>, <&sdma 47 21 0>;
338                                         dma-names = "rx", "tx";
339                                         dma-source = <&gpr 0 14 0 15>;
340                                         status = "disabled";
341                                 };
342
343                                 sai1: sai@02028000 {
344                                         compatible = "fsl,imx6ul-sai",
345                                                      "fsl,imx6sx-sai";
346                                         reg = <0x02028000 0x4000>;
347                                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
348                                         clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
349                                                  <&clks IMX6UL_CLK_DUMMY>,
350                                                  <&clks IMX6UL_CLK_SAI1>,
351                                                  <&clks 0>, <&clks 0>;
352                                         clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
353                                         dma-names = "rx", "tx";
354                                         dmas = <&sdma 35 24 0>, <&sdma 36 24 0>;
355                                         status = "disabled";
356                                 };
357
358                                 sai2: sai@0202c000 {
359                                         compatible = "fsl,imx6ul-sai",
360                                                      "fsl,imx6sx-sai";
361                                         reg = <0x0202c000 0x4000>;
362                                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
363                                         clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
364                                                  <&clks IMX6UL_CLK_DUMMY>,
365                                                  <&clks IMX6UL_CLK_SAI2>,
366                                                  <&clks 0>, <&clks 0>;
367                                         clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
368                                         dma-names = "rx", "tx";
369                                         dmas = <&sdma 37 24 0>, <&sdma 38 24 0>;
370                                         status = "disabled";
371                                 };
372
373                                 sai3: sai@02030000 {
374                                         compatible = "fsl,imx6ul-sai",
375                                                      "fsl,imx6sx-sai";
376                                         reg = <0x02030000 0x4000>;
377                                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
378                                         clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
379                                                  <&clks IMX6UL_CLK_DUMMY>,
380                                                  <&clks IMX6UL_CLK_SAI3>,
381                                                  <&clks 0>, <&clks 0>;
382                                         clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
383                                         dma-names = "rx", "tx";
384                                         dmas = <&sdma 39 24 0>, <&sdma 40 24 0>;
385                                         status = "disabled";
386                                 };
387
388                                 asrc: asrc@02034000 {
389                                         compatible = "fsl,imx53-asrc";
390                                         reg = <0x02034000 0x4000>;
391                                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
392                                         clocks = <&clks IMX6UL_CLK_ASRC_IPG>,
393                                                 <&clks IMX6UL_CLK_ASRC_MEM>, <&clks 0>,
394                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
395                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
396                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
397                                                 <&clks IMX6UL_CLK_SPDIF>, <&clks 0>, <&clks 0>,
398                                                 <&clks IMX6UL_CLK_SPBA>;
399                                         clock-names = "mem", "ipg", "asrck_0",
400                                                 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
401                                                 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
402                                                 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
403                                                 "asrck_d", "asrck_e", "asrck_f", "dma";
404                                         dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
405                                                 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
406                                         dma-names = "rxa", "rxb", "rxc",
407                                                     "txa", "txb", "txc";
408                                         fsl,asrc-rate  = <48000>;
409                                         fsl,asrc-width = <16>;
410                                         status = "okay";
411                                 };
412                         };
413
414                         tsc: tsc@02040000 {
415                                 compatible = "fsl,imx6ul-tsc";
416                                 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
417                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
418                                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
419                                 clocks = <&clks IMX6UL_CLK_IPG>,
420                                          <&clks IMX6UL_CLK_ADC2>;
421                                 clock-names = "tsc", "adc";
422                                 status = "disabled";
423                         };
424
425                         pwm1: pwm@02080000 {
426                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
427                                 reg = <0x02080000 0x4000>;
428                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
429                                 clocks = <&clks IMX6UL_CLK_PWM1>,
430                                          <&clks IMX6UL_CLK_PWM1>;
431                                 clock-names = "ipg", "per";
432                                 #pwm-cells = <2>;
433                         };
434
435                         pwm2: pwm@02084000 {
436                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
437                                 reg = <0x02084000 0x4000>;
438                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
439                                 clocks = <&clks IMX6UL_CLK_DUMMY>,
440                                          <&clks IMX6UL_CLK_DUMMY>;
441                                 clock-names = "ipg", "per";
442                                 #pwm-cells = <2>;
443                         };
444
445                         pwm3: pwm@02088000 {
446                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
447                                 reg = <0x02088000 0x4000>;
448                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
449                                 clocks = <&clks IMX6UL_CLK_PWM3>,
450                                          <&clks IMX6UL_CLK_PWM3>;
451                                 clock-names = "ipg", "per";
452                                 #pwm-cells = <2>;
453                         };
454
455                         pwm4: pwm@0208c000 {
456                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
457                                 reg = <0x0208c000 0x4000>;
458                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
459                                 clocks = <&clks IMX6UL_CLK_DUMMY>,
460                                          <&clks IMX6UL_CLK_DUMMY>;
461                                 clock-names = "ipg", "per";
462                                 #pwm-cells = <2>;
463                         };
464
465                         flexcan1: can@02090000 {
466                                 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
467                                 reg = <0x02090000 0x4000>;
468                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
469                                 clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
470                                          <&clks IMX6UL_CLK_CAN1_SERIAL>;
471                                 clock-names = "ipg", "per";
472                                 stop-mode = <&gpr 0x10 1 0x10 17>;
473                                 status = "disabled";
474                         };
475
476                         flexcan2: can@02094000 {
477                                 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
478                                 reg = <0x02094000 0x4000>;
479                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
480                                 clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
481                                          <&clks IMX6UL_CLK_CAN2_SERIAL>;
482                                 clock-names = "ipg", "per";
483                                 stop-mode = <&gpr 0x10 2 0x10 18>;
484                                 status = "disabled";
485                         };
486
487                         gpt1: gpt@02098000 {
488                                 compatible = "fsl,imx6ul-gpt", "fsl,imx31-gpt";
489                                 reg = <0x02098000 0x4000>;
490                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
491                                 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
492                                          <&clks IMX6UL_CLK_GPT1_SERIAL>;
493                                 clock-names = "ipg", "per";
494                         };
495
496                         gpio1: gpio@0209c000 {
497                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
498                                 reg = <0x0209c000 0x4000>;
499                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
500                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
501                                 gpio-controller;
502                                 #gpio-cells = <2>;
503                                 interrupt-controller;
504                                 #interrupt-cells = <2>;
505                         };
506
507                         gpio2: gpio@020a0000 {
508                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
509                                 reg = <0x020a0000 0x4000>;
510                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
511                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
512                                 gpio-controller;
513                                 #gpio-cells = <2>;
514                                 interrupt-controller;
515                                 #interrupt-cells = <2>;
516                         };
517
518                         gpio3: gpio@020a4000 {
519                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
520                                 reg = <0x020a4000 0x4000>;
521                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
522                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
523                                 gpio-controller;
524                                 #gpio-cells = <2>;
525                                 interrupt-controller;
526                                 #interrupt-cells = <2>;
527                         };
528
529                         gpio4: gpio@020a8000 {
530                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
531                                 reg = <0x020a8000 0x4000>;
532                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
533                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
534                                 gpio-controller;
535                                 #gpio-cells = <2>;
536                                 interrupt-controller;
537                                 #interrupt-cells = <2>;
538                         };
539
540                         gpio5: gpio@020ac000 {
541                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
542                                 reg = <0x020ac000 0x4000>;
543                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
544                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
545                                 gpio-controller;
546                                 #gpio-cells = <2>;
547                                 interrupt-controller;
548                                 #interrupt-cells = <2>;
549                         };
550
551                         snvslp: snvs@020b0000 {
552                                 compatible = "fsl,imx6ul-snvs";
553                                 reg = <0x020b0000 0x4000>;
554                                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
555                         };
556
557                         fec2: ethernet@020b4000 {
558                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
559                                 reg = <0x020b4000 0x4000>;
560                                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
561                                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
562                                 clocks = <&clks IMX6UL_CLK_ENET>,
563                                          <&clks IMX6UL_CLK_ENET_AHB>,
564                                          <&clks IMX6UL_CLK_ENET_PTP>,
565                                          <&clks IMX6UL_CLK_ENET2_REF_125M>,
566                                          <&clks IMX6UL_CLK_ENET2_REF_125M>;
567                                 clock-names = "ipg", "ahb", "ptp",
568                                               "enet_clk_ref", "enet_out";
569                                 stop-mode = <&gpr 0x10 4>;
570                                 fsl,num-tx-queues=<1>;
571                                 fsl,num-rx-queues=<1>;
572                                 fsl,magic-packet;
573                                 fsl,wakeup_irq = <0>;
574                                 status = "disabled";
575                         };
576
577                         kpp: kpp@020b8000 {
578                                 compatible = "fsl,imx6ul-kpp", "fsl,imx21-kpp";
579                                 reg = <0x020b8000 0x4000>;
580                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
581                                 clocks = <&clks IMX6UL_CLK_DUMMY>;
582                                 status = "disabled";
583                         };
584
585                         wdog1: wdog@020bc000 {
586                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
587                                 reg = <0x020bc000 0x4000>;
588                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
589                                 clocks = <&clks IMX6UL_CLK_WDOG1>;
590                         };
591
592                         wdog2: wdog@020c0000 {
593                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
594                                 reg = <0x020c0000 0x4000>;
595                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
596                                 clocks = <&clks IMX6UL_CLK_WDOG2>;
597                                 status = "disabled";
598                         };
599
600                         clks: ccm@020c4000 {
601                                 compatible = "fsl,imx6ul-ccm";
602                                 reg = <0x020c4000 0x4000>;
603                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
604                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
605                                 #clock-cells = <1>;
606                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
607                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
608                         };
609
610                         anatop: anatop@020c8000 {
611                                 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
612                                              "syscon", "simple-bus";
613                                 reg = <0x020c8000 0x1000>;
614                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
615                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
616                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
617
618                                 reg_3p0: regulator-3p0@120 {
619                                         compatible = "fsl,anatop-regulator";
620                                         regulator-name = "vdd3p0";
621                                         regulator-min-microvolt = <2625000>;
622                                         regulator-max-microvolt = <3400000>;
623                                         anatop-reg-offset = <0x120>;
624                                         anatop-vol-bit-shift = <8>;
625                                         anatop-vol-bit-width = <5>;
626                                         anatop-min-bit-val = <0>;
627                                         anatop-min-voltage = <2625000>;
628                                         anatop-max-voltage = <3400000>;
629                                         anatop-enable-bit = <0>;
630                                 };
631
632                                 reg_arm: regulator-vddcore@140 {
633                                         compatible = "fsl,anatop-regulator";
634                                         regulator-name = "cpu";
635                                         regulator-min-microvolt = <725000>;
636                                         regulator-max-microvolt = <1450000>;
637                                         regulator-always-on;
638                                         anatop-reg-offset = <0x140>;
639                                         anatop-vol-bit-shift = <0>;
640                                         anatop-vol-bit-width = <5>;
641                                         anatop-delay-reg-offset = <0x170>;
642                                         anatop-delay-bit-shift = <24>;
643                                         anatop-delay-bit-width = <2>;
644                                         anatop-min-bit-val = <1>;
645                                         anatop-min-voltage = <725000>;
646                                         anatop-max-voltage = <1450000>;
647                                 };
648
649                                 reg_soc: regulator-vddsoc@140 {
650                                         compatible = "fsl,anatop-regulator";
651                                         regulator-name = "vddsoc";
652                                         regulator-min-microvolt = <725000>;
653                                         regulator-max-microvolt = <1450000>;
654                                         regulator-always-on;
655                                         anatop-reg-offset = <0x140>;
656                                         anatop-vol-bit-shift = <18>;
657                                         anatop-vol-bit-width = <5>;
658                                         anatop-delay-reg-offset = <0x170>;
659                                         anatop-delay-bit-shift = <28>;
660                                         anatop-delay-bit-width = <2>;
661                                         anatop-min-bit-val = <1>;
662                                         anatop-min-voltage = <725000>;
663                                         anatop-max-voltage = <1450000>;
664                                 };
665                         };
666
667                         usbphy1: usbphy@020c9000 {
668                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
669                                 reg = <0x020c9000 0x1000>;
670                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
671                                 clocks = <&clks IMX6UL_CLK_USBPHY1>;
672                                 phy-3p0-supply = <&reg_3p0>;
673                                 fsl,anatop = <&anatop>;
674                         };
675
676                         usbphy2: usbphy@020ca000 {
677                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
678                                 reg = <0x020ca000 0x1000>;
679                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
680                                 clocks = <&clks IMX6UL_CLK_USBPHY2>;
681                                 phy-3p0-supply = <&reg_3p0>;
682                                 fsl,anatop = <&anatop>;
683                         };
684
685                         tempmon: tempmon {
686                                 compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
687                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
688                                 fsl,tempmon = <&anatop>;
689                                 fsl,tempmon-data = <&ocotp>;
690                                 clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
691                         };
692
693                         snvs: snvs@020cc000 {
694                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
695                                 reg = <0x020cc000 0x4000>;
696
697                                 snvs_rtc: snvs-rtc-lp {
698                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
699                                         regmap = <&snvs>;
700                                         offset = <0x34>;
701                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
702                                 };
703
704                                 snvs_poweroff: snvs-poweroff {
705                                         compatible = "syscon-poweroff";
706                                         regmap = <&snvs>;
707                                         offset = <0x38>;
708                                         mask = <0x61>;
709                                 };
710
711                                 snvs_pwrkey: snvs-powerkey {
712                                         compatible = "fsl,sec-v4.0-pwrkey";
713                                         regmap = <&snvs>;
714                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
715                                         linux,keycode = <KEY_POWER>;
716                                         wakeup;
717                                 };
718                         };
719
720                         epit1: epit@020d0000 {
721                                 reg = <0x020d0000 0x4000>;
722                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
723                         };
724
725                         epit2: epit@020d4000 {
726                                 reg = <0x020d4000 0x4000>;
727                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
728                         };
729
730                         src: src@020d8000 {
731                                 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
732                                 reg = <0x020d8000 0x4000>;
733                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
734                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
735                                 #reset-cells = <1>;
736                         };
737
738                         gpc: gpc@020dc000 {
739                                 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
740                                 reg = <0x020dc000 0x4000>;
741                                 interrupt-controller;
742                                 #interrupt-cells = <3>;
743                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
744                                 interrupt-parent = <&intc>;
745                                 fsl,mf-mix-wakeup-irq = <0xfc00000 0x7d00 0x0 0x1400640>;
746                         };
747
748                         iomuxc: iomuxc@020e0000 {
749                                 compatible = "fsl,imx6ul-iomuxc";
750                                 reg = <0x020e0000 0x4000>;
751                         };
752
753                         gpr: iomuxc-gpr@020e4000 {
754                                 compatible = "fsl,imx6ul-iomuxc-gpr", "syscon";
755                                 reg = <0x020e4000 0x4000>;
756                         };
757
758                         mqs: mqs {
759                                 compatible = "fsl,imx6sx-mqs";
760                                 gpr = <&gpr>;
761                                 status = "disabled";
762                         };
763
764                         gpt2: gpt@020e8000 {
765                                 compatible = "fsl,imx6ul-gpt", "fsl,imx31-gpt";
766                                 reg = <0x020e8000 0x4000>;
767                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
768                                 clocks = <&clks IMX6UL_CLK_DUMMY>,
769                                          <&clks IMX6UL_CLK_DUMMY>;
770                                 clock-names = "ipg", "per";
771                         };
772
773                         sdma: sdma@020ec000 {
774                                 compatible = "fsl,imx6ul-sdma", "fsl,imx35-sdma";
775                                 reg = <0x020ec000 0x4000>;
776                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
777                                 clocks = <&clks IMX6UL_CLK_SDMA>,
778                                          <&clks IMX6UL_CLK_SDMA>;
779                                 clock-names = "ipg", "ahb";
780                                 #dma-cells = <3>;
781                                 iram = <&ocram>;
782                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
783                         };
784
785                         pwm5: pwm@020f0000 {
786                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
787                                 reg = <0x020f0000 0x4000>;
788                                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
789                                 clocks = <&clks IMX6UL_CLK_DUMMY>,
790                                          <&clks IMX6UL_CLK_DUMMY>;
791                                 clock-names = "ipg", "per";
792                                 #pwm-cells = <2>;
793                         };
794
795                         pwm6: pwm@020f4000 {
796                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
797                                 reg = <0x020f4000 0x4000>;
798                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
799                                 clocks = <&clks IMX6UL_CLK_DUMMY>,
800                                          <&clks IMX6UL_CLK_DUMMY>;
801                                 clock-names = "ipg", "per";
802                                 #pwm-cells = <2>;
803                         };
804
805                         pwm7: pwm@020f8000 {
806                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
807                                 reg = <0x020f8000 0x4000>;
808                                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
809                                 clocks = <&clks IMX6UL_CLK_DUMMY>,
810                                          <&clks IMX6UL_CLK_DUMMY>;
811                                 clock-names = "ipg", "per";
812                                 #pwm-cells = <2>;
813                         };
814
815                         pwm8: pwm@020fc000 {
816                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
817                                 reg = <0x020fc000 0x4000>;
818                                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
819                                 clocks = <&clks IMX6UL_CLK_DUMMY>,
820                                          <&clks IMX6UL_CLK_DUMMY>;
821                                 clock-names = "ipg", "per";
822                                 #pwm-cells = <2>;
823                         };
824                 };
825
826                 aips2: aips-bus@02100000 {
827                         compatible = "fsl,aips-bus", "simple-bus";
828                         #address-cells = <1>;
829                         #size-cells = <1>;
830                         reg = <0x02100000 0x100000>;
831                         ranges;
832
833                         usbotg1: usb@02184000 {
834                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
835                                 reg = <0x02184000 0x200>;
836                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
837                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
838                                 fsl,usbphy = <&usbphy1>;
839                                 fsl,usbmisc = <&usbmisc 0>;
840                                 fsl,anatop = <&anatop>;
841                                 ahb-burst-config = <0x0>;
842                                 tx-burst-size-dword = <0x10>;
843                                 rx-burst-size-dword = <0x10>;
844                                 status = "disabled";
845                         };
846
847                         usbotg2: usb@02184200 {
848                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
849                                 reg = <0x02184200 0x200>;
850                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
851                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
852                                 fsl,usbphy = <&usbphy2>;
853                                 fsl,usbmisc = <&usbmisc 1>;
854                                 ahb-burst-config = <0x0>;
855                                 tx-burst-size-dword = <0x10>;
856                                 rx-burst-size-dword = <0x10>;
857                                 status = "disabled";
858                         };
859
860                         usbmisc: usbmisc@02184800 {
861                                 #index-cells = <1>;
862                                 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
863                                 reg = <0x02184800 0x200>;
864                         };
865
866                         fec1: ethernet@02188000 {
867                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
868                                 reg = <0x02188000 0x4000>;
869                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
870                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
871                                 clocks = <&clks IMX6UL_CLK_ENET>,
872                                          <&clks IMX6UL_CLK_ENET_AHB>,
873                                          <&clks IMX6UL_CLK_ENET_PTP>,
874                                          <&clks IMX6UL_CLK_ENET_REF>,
875                                          <&clks IMX6UL_CLK_ENET_REF>;
876                                 clock-names = "ipg", "ahb", "ptp",
877                                               "enet_clk_ref", "enet_out";
878                                 stop-mode = <&gpr 0x10 3>;
879                                 fsl,num-tx-queues=<1>;
880                                 fsl,num-rx-queues=<1>;
881                                 fsl,magic-packet;
882                                 fsl,wakeup_irq = <0>;
883                                 status = "disabled";
884                         };
885
886                         usdhc1: usdhc@02190000 {
887                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
888                                 reg = <0x02190000 0x4000>;
889                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
890                                 clocks = <&clks IMX6UL_CLK_USDHC1>,
891                                          <&clks IMX6UL_CLK_USDHC1>,
892                                          <&clks IMX6UL_CLK_USDHC1>;
893                                 clock-names = "ipg", "ahb", "per";
894                                 bus-width = <4>;
895                                 fsl,tuning-step= <2>;
896                                 status = "disabled";
897                         };
898
899                         usdhc2: usdhc@02194000 {
900                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
901                                 reg = <0x02194000 0x4000>;
902                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
903                                 clocks = <&clks IMX6UL_CLK_USDHC2>,
904                                          <&clks IMX6UL_CLK_USDHC2>,
905                                          <&clks IMX6UL_CLK_USDHC2>;
906                                 clock-names = "ipg", "ahb", "per";
907                                 bus-width = <4>;
908                                 fsl,tuning-step= <2>;
909                                 status = "disabled";
910                         };
911
912                         adc1: adc@02198000 {
913                                 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
914                                 reg = <0x02198000 0x4000>;
915                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
916                                 clocks = <&clks IMX6UL_CLK_ADC1>;
917                                 num-channels = <2>;
918                                 clock-names = "adc";
919                                 status = "disabled";
920                         };
921
922                         i2c1: i2c@021a0000 {
923                                 #address-cells = <1>;
924                                 #size-cells = <0>;
925                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
926                                 reg = <0x021a0000 0x4000>;
927                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
928                                 clocks = <&clks IMX6UL_CLK_I2C1>;
929                                 status = "disabled";
930                         };
931
932                         i2c2: i2c@021a4000 {
933                                 #address-cells = <1>;
934                                 #size-cells = <0>;
935                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
936                                 reg = <0x021a4000 0x4000>;
937                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
938                                 clocks = <&clks IMX6UL_CLK_I2C2>;
939                                 status = "disabled";
940                         };
941
942                         i2c3: i2c@021a8000 {
943                                 #address-cells = <1>;
944                                 #size-cells = <0>;
945                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
946                                 reg = <0x021a8000 0x4000>;
947                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
948                                 clocks = <&clks IMX6UL_CLK_I2C3>;
949                                 status = "disabled";
950                         };
951
952                         romcp@021ac000 {
953                                 compatible = "fsl,imx6ul-romcp", "syscon";
954                                 reg = <0x021ac000 0x4000>;
955                         };
956
957                         mmdc: mmdc@021b0000 {
958                                 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
959                                 reg = <0x021b0000 0x4000>;
960                         };
961
962                         weim: weim@021b8000 {
963                                 compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim";
964                                 reg = <0x021b8000 0x4000>;
965                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
966                                 clocks = <&clks IMX6UL_CLK_DUMMY>;
967                         };
968
969                         ocotp: ocotp-ctrl@021bc000 {
970                                 compatible = "fsl,imx6ull-ocotp", "syscon";
971                                 reg = <0x021bc000 0x4000>;
972                                 clocks = <&clks IMX6UL_CLK_OCOTP>;
973                         };
974
975                         csu: csu@021c0000 {
976                                 compatible = "fsl,imx6ul-csu";
977                                 reg = <0x021c0000 0x4000>;
978                                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
979                                 status = "disabled";
980                         };
981
982                         csi: csi@021c4000 {
983                                 compatible = "fsl,imx6ul-csi", "fsl,imx6s-csi";
984                                 reg = <0x021c4000 0x4000>;
985                                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
986                                 clocks = <&clks IMX6UL_CLK_DUMMY>,
987                                         <&clks IMX6UL_CLK_CSI>,
988                                         <&clks IMX6UL_CLK_DUMMY>;
989                                 clock-names = "disp-axi", "csi_mclk", "disp_dcic";
990                                 status = "disabled";
991                         };
992
993                         lcdif: lcdif@021c8000 {
994                                 compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
995                                 reg = <0x021c8000 0x4000>;
996                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
997                                 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
998                                          <&clks IMX6UL_CLK_LCDIF_APB>,
999                                          <&clks IMX6UL_CLK_DUMMY>;
1000                                 clock-names = "pix", "axi", "disp_axi";
1001                                 status = "disabled";
1002                         };
1003
1004                         pxp: pxp@021cc000 {
1005                                 compatible = "fsl,imx6ull-pxp-dma", "fsl,imx7d-pxp-dma";
1006                                 reg = <0x021cc000 0x4000>;
1007                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1008                                         <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1009                                 clocks = <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_PXP>;
1010                                 clock-names = "pxp_ipg", "pxp_axi";
1011                                 status = "disabled";
1012                         };
1013
1014                         qspi: qspi@021e0000 {
1015                                 #address-cells = <1>;
1016                                 #size-cells = <0>;
1017                                 compatible = "fsl,imx6ull-qspi", "fsl,imx6ul-qspi";
1018                                 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1019                                 reg-names = "QuadSPI", "QuadSPI-memory";
1020                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1021                                 clocks = <&clks IMX6UL_CLK_QSPI>,
1022                                          <&clks IMX6UL_CLK_QSPI>;
1023                                 clock-names = "qspi_en", "qspi";
1024                                 status = "disabled";
1025                         };
1026
1027                         uart2: serial@021e8000 {
1028                                 compatible = "fsl,imx6ul-uart",
1029                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1030                                 reg = <0x021e8000 0x4000>;
1031                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1032                                 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
1033                                          <&clks IMX6UL_CLK_UART2_SERIAL>;
1034                                 clock-names = "ipg", "per";
1035                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1036                                 dma-names = "rx", "tx";
1037                                 status = "disabled";
1038                         };
1039
1040                         uart3: serial@021ec000 {
1041                                 compatible = "fsl,imx6ul-uart",
1042                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1043                                 reg = <0x021ec000 0x4000>;
1044                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1045                                 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
1046                                          <&clks IMX6UL_CLK_UART3_SERIAL>;
1047                                 clock-names = "ipg", "per";
1048                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1049                                 dma-names = "rx", "tx";
1050                                 status = "disabled";
1051                         };
1052
1053                         uart4: serial@021f0000 {
1054                                 compatible = "fsl,imx6ul-uart",
1055                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1056                                 reg = <0x021f0000 0x4000>;
1057                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1058                                 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
1059                                          <&clks IMX6UL_CLK_UART4_SERIAL>;
1060                                 clock-names = "ipg", "per";
1061                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1062                                 dma-names = "rx", "tx";
1063                                 status = "disabled";
1064                         };
1065
1066                         uart5: serial@021f4000 {
1067                                 compatible = "fsl,imx6ul-uart",
1068                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1069                                 reg = <0x021f4000 0x4000>;
1070                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1071                                 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
1072                                          <&clks IMX6UL_CLK_UART5_SERIAL>;
1073                                 clock-names = "ipg", "per";
1074                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1075                                 dma-names = "rx", "tx";
1076                                 status = "disabled";
1077                         };
1078
1079                         i2c4: i2c@021f8000 {
1080                                 #address-cells = <1>;
1081                                 #size-cells = <0>;
1082                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
1083                                 reg = <0x021f8000 0x4000>;
1084                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1085                                 clocks = <&clks IMX6UL_CLK_I2C4>;
1086                                 status = "disabled";
1087                         };
1088
1089                         uart6: serial@021fc000 {
1090                                 compatible = "fsl,imx6ul-uart",
1091                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1092                                 reg = <0x021fc000 0x4000>;
1093                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1094                                 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
1095                                          <&clks IMX6UL_CLK_UART6_SERIAL>;
1096                                 clock-names = "ipg", "per";
1097                                 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1098                                 dma-names = "rx", "tx";
1099                                 status = "disabled";
1100                         };
1101                 };
1102
1103                 aips3: aips-bus@02200000 {
1104                         compatible = "fsl,aips-bus", "simple-bus";
1105                         #address-cells = <1>;
1106                         #size-cells = <1>;
1107                         reg = <0x02200000 0x100000>;
1108                         ranges;
1109
1110                         dcp: dcp@02280000 {
1111                                 reg = <0x02280000 0x4000>;
1112                                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1113                                              <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1114                                              <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1115                                 /*clocks = <&clks IMX6UL_CLK_DCP>;*/
1116                                 clock-names = "dcp";
1117                                 status = "disabled";
1118                         };
1119
1120                         rngb: rngb@02284000 {
1121                                 reg = <0x02284000 0x4000>;
1122                                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1123                         };
1124
1125                         uart8: serial@02288000 {
1126                                 compatible = "fsl,imx6ul-uart",
1127                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1128                                 reg = <0x02288000 0x4000>;
1129                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1130                                 clocks = <&clks IMX6UL_CLK_UART8_IPG>,
1131                                          <&clks IMX6UL_CLK_UART8_SERIAL>;
1132                                 clock-names = "ipg", "per";
1133                                 dmas = <&sdma 45 4 0>, <&sdma 46 4 0>;
1134                                 dma-names = "rx", "tx";
1135                                 status = "disabled";
1136                         };
1137
1138                         epdc: epdc@0228c000 {
1139                                 compatible = "fsl,imx7d-epdc";
1140                                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1141                                 reg = <0x0228c000 0x4000>;
1142                                 clocks = <&clks IMX6UL_CLK_EPDC_ACLK>,
1143                                          <&clks IMX6UL_CLK_EPDC_PIX>;
1144                                 clock-names = "epdc_axi", "epdc_pix";
1145                                 /* Need to fix epdc-ram */
1146                                 /* epdc-ram = <&gpr 0x4 30>; */
1147                                 status = "disabled";
1148                         };
1149
1150                         iomuxc_snvs: iomuxc-snvs@02290000 {
1151                                 compatible = "fsl,imx6ull-iomuxc-snvs";
1152                                 reg = <0x02290000 0x10000>;
1153                         };
1154
1155                         snvs_gpr: snvs-gpr@0x02294000 {
1156                                 compatible = "fsl, imx6ull-snvs-gpr";
1157                                 reg = <0x02294000 0x10000>;
1158                         };
1159                 };
1160         };
1161 };