arch/arm/dts/imx6ull.dtsi

   1 /*
   2  * Copyright 2015-2016 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <dt-bindings/clock/imx6ul-clock.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/input/input.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include "imx6ull-pinfunc.h"
  14 #include "imx6ull-pinfunc-snvs.h"
  15 #include "skeleton.dtsi"
  16
  17 / {
  18         aliases {
  19                 can0 = &flexcan1;
  20                 can1 = &flexcan2;
  21                 ethernet0 = &fec1;
  22                 ethernet1 = &fec2;
  23                 gpio0 = &gpio1;
  24                 gpio1 = &gpio2;
  25                 gpio2 = &gpio3;
  26                 gpio3 = &gpio4;
  27                 gpio4 = &gpio5;
  28                 i2c0 = &i2c1;
  29                 i2c1 = &i2c2;
  30                 i2c2 = &i2c3;
  31                 i2c3 = &i2c4;
  32                 mmc0 = &usdhc1;
  33                 mmc1 = &usdhc2;
  34                 serial0 = &uart1;
  35                 serial1 = &uart2;
  36                 serial2 = &uart3;
  37                 serial3 = &uart4;
  38                 serial4 = &uart5;
  39                 serial5 = &uart6;
  40                 serial6 = &uart7;
  41                 serial7 = &uart8;
  42                 spi0 = &qspi;
  43                 spi1 = &ecspi1;
  44                 spi2 = &ecspi2;
  45                 spi3 = &ecspi3;
  46                 spi4 = &ecspi4;
  47                 usbphy0 = &usbphy1;
  48                 usbphy1 = &usbphy2;
  49                 usb0 = &usbotg1;
  50                 usb1 = &usbotg2;
  51         };
  52
  53         cpus {
  54                 #address-cells = <1>;
  55                 #size-cells = <0>;
  56
  57                 cpu0: cpu@0 {
  58                         compatible = "arm,cortex-a7";
  59                         device_type = "cpu";
  60                         reg = <0>;
  61                         clock-latency = <61036>; /* two CLK32 periods */
  62                         operating-points = <
  63                                 /* kHz  uV */
  64                                 528000  1175000
  65                                 99000   950000
  66                         >;
  67                         fsl,soc-operating-points = <
  68                                 /* KHz  uV */
  69                                 528000  1175000
  70                                 99000   1175000
  71                         >;
  72                         clocks = <&clks IMX6UL_CLK_ARM>,
  73                                  <&clks IMX6UL_CLK_PLL2_BUS>,
  74                                  <&clks IMX6UL_CLK_PLL2_PFD2>,
  75                                  <&clks IMX6UL_CA7_SECONDARY_SEL>,
  76                                  <&clks IMX6UL_CLK_STEP>,
  77                                  <&clks IMX6UL_CLK_PLL1_SW>,
  78                                  <&clks IMX6UL_CLK_PLL1_SYS>,
  79                                  <&clks IMX6UL_PLL1_BYPASS>,
  80                                  <&clks IMX6UL_CLK_PLL1>,
  81                                  <&clks IMX6UL_PLL1_BYPASS_SRC>,
  82                                  <&clks IMX6UL_CLK_OSC>;
  83                         clock-names = "arm", "pll2_bus",  "pll2_pfd2_396m", "secondary_sel", "step",
  84                                       "pll1_sw", "pll1_sys", "pll1_bypass", "pll1", "pll1_bypass_src", "osc";
  85                 };
  86         };
  87
  88         intc: interrupt-controller@00a01000 {
  89                 compatible = "arm,cortex-a7-gic";
  90                 #interrupt-cells = <3>;
  91                 interrupt-controller;
  92                 reg = <0x00a01000 0x1000>,
  93                       <0x00a02000 0x100>;
  94         };
  95
  96         clocks {
  97                 #address-cells = <1>;
  98                 #size-cells = <0>;
  99
 100                 ckil: clock@0 {
 101                         compatible = "fixed-clock";
 102                         reg = <0>;
 103                         #clock-cells = <0>;
 104                         clock-frequency = <32768>;
 105                         clock-output-names = "ckil";
 106                 };
 107
 108                 osc: clock@1 {
 109                         compatible = "fixed-clock";
 110                         reg = <1>;
 111                         #clock-cells = <0>;
 112                         clock-frequency = <24000000>;
 113                         clock-output-names = "osc";
 114                 };
 115
 116                 ipp_di0: clock@2 {
 117                         compatible = "fixed-clock";
 118                         reg = <2>;
 119                         #clock-cells = <0>;
 120                         clock-frequency = <0>;
 121                         clock-output-names = "ipp_di0";
 122                 };
 123
 124                 ipp_di1: clock@3 {
 125                         compatible = "fixed-clock";
 126                         reg = <3>;
 127                         #clock-cells = <0>;
 128                         clock-frequency = <0>;
 129                         clock-output-names = "ipp_di1";
 130                 };
 131         };
 132
 133         soc {
 134                 #address-cells = <1>;
 135                 #size-cells = <1>;
 136                 compatible = "simple-bus";
 137                 interrupt-parent = <&gpc>;
 138                 ranges;
 139
 140                 busfreq {
 141                         compatible = "fsl,imx_busfreq";
 142                         clocks = <&clks IMX6UL_CLK_PLL2_PFD2>, <&clks IMX6UL_CLK_PLL2_198M>,
 143                                  <&clks IMX6UL_CLK_PLL2_BUS>, <&clks IMX6UL_CLK_ARM>,
 144                                  <&clks IMX6UL_CLK_PLL3_USB_OTG>, <&clks IMX6UL_CLK_PERIPH>,
 145                                  <&clks IMX6UL_CLK_PERIPH_PRE>, <&clks IMX6UL_CLK_PERIPH_CLK2>,
 146                                  <&clks IMX6UL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6UL_CLK_OSC>,
 147                                  <&clks IMX6UL_CLK_AHB>, <&clks IMX6UL_CLK_AXI>,
 148                                  <&clks IMX6UL_CLK_PERIPH2>, <&clks IMX6UL_CLK_PERIPH2_PRE>,
 149                                  <&clks IMX6UL_CLK_PERIPH2_CLK2>, <&clks IMX6UL_CLK_PERIPH2_CLK2_SEL>,
 150                                  <&clks IMX6UL_CLK_STEP>, <&clks IMX6UL_CLK_MMDC_P0_FAST>, <&clks IMX6UL_PLL1_BYPASS_SRC>,
 151                                  <&clks IMX6UL_PLL1_BYPASS>, <&clks IMX6UL_CLK_PLL1_SYS>, <&clks IMX6UL_CLK_PLL1_SW>,
 152                                  <&clks IMX6UL_CLK_PLL1>;
 153                         clock-names = "pll2_pfd2_396m", "pll2_198m", "pll2_bus", "arm", "pll3_usb_otg",
 154                                       "periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc",
 155                                       "ahb", "ocram", "periph2", "periph2_pre", "periph2_clk2", "periph2_clk2_sel",
 156                                       "step", "mmdc", "pll1_bypass_src", "pll1_bypass", "pll1_sys", "pll1_sw", "pll1";
 157                         fsl,max_ddr_freq = <400000000>;
 158                 };
 159
 160                 pmu {
 161                         compatible = "arm,cortex-a7-pmu";
 162                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 163                         status = "disabled";
 164                 };
 165
 166                 ocrams: sram@00900000 {
 167                         compatible = "fsl,lpm-sram";
 168                         reg = <0x00900000 0x4000>;
 169                 };
 170
 171                 ocrams_ddr: sram@00904000 {
 172                         compatible = "fsl,ddr-lpm-sram";
 173                         reg = <0x00904000 0x1000>;
 174                 };
 175
 176                 ocram: sram@00905000 {
 177                         compatible = "mmio-sram";
 178                         reg = <0x00905000 0x1B000>;
 179                 };
 180
 181                 dma_apbh: dma-apbh@01804000 {
 182                         compatible = "fsl,imx6ul-dma-apbh", "fsl,imx28-dma-apbh";
 183                         reg = <0x01804000 0x2000>;
 184                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 185                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 186                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 187                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 188                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
 189                         #dma-cells = <1>;
 190                         dma-channels = <4>;
 191                         clocks = <&clks IMX6UL_CLK_APBHDMA>;
 192                 };
 193
 194                 gpmi: gpmi-nand@01806000{
 195                         compatible = "fsl,imx6q-gpmi-nand";
 196                         #address-cells = <1>;
 197                         #size-cells = <1>;
 198                         reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
 199                         reg-names = "gpmi-nand", "bch";
 200                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 201                         interrupt-names = "bch";
 202                         clocks = <&clks IMX6UL_CLK_GPMI_IO>,
 203                                  <&clks IMX6UL_CLK_GPMI_APB>,
 204                                  <&clks IMX6UL_CLK_GPMI_BCH>,
 205                                  <&clks IMX6UL_CLK_GPMI_BCH_APB>,
 206                                  <&clks IMX6UL_CLK_PER_BCH>;
 207                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 208                                       "gpmi_bch_apb", "per1_bch";
 209                         dmas = <&dma_apbh 0>;
 210                         dma-names = "rx-tx";
 211                         status = "disabled";
 212                 };
 213
 214                 aips1: aips-bus@02000000 {
 215                         compatible = "fsl,aips-bus", "simple-bus";
 216                         #address-cells = <1>;
 217                         #size-cells = <1>;
 218                         reg = <0x02000000 0x100000>;
 219                         ranges;
 220
 221                         spba-bus@02000000 {
 222                                 compatible = "fsl,spba-bus", "simple-bus";
 223                                 #address-cells = <1>;
 224                                 #size-cells = <1>;
 225                                 reg = <0x02000000 0x40000>;
 226                                 ranges;
 227
 228                                 spdif: spdif@02004000 {
 229                                         compatible = "fsl,imx6ul-spdif", "fsl,imx35-spdif";
 230                                         reg = <0x02004000 0x4000>;
 231                                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 232                                         dmas = <&sdma 41 18 0>,
 233                                                <&sdma 42 18 0>;
 234                                         dma-names = "rx", "tx";
 235                                         clocks = <&clks IMX6UL_CLK_SPDIF_GCLK>,
 236                                                  <&clks IMX6UL_CLK_OSC>,
 237                                                  <&clks IMX6UL_CLK_SPDIF>,
 238                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>,
 239                                                  <&clks IMX6UL_CLK_IPG>,
 240                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>,
 241                                                  <&clks IMX6UL_CLK_SPBA>;
 242                                         clock-names = "core", "rxtx0",
 243                                                       "rxtx1", "rxtx2",
 244                                                       "rxtx3", "rxtx4",
 245                                                       "rxtx5", "rxtx6",
 246                                                       "rxtx7", "dma";
 247                                         status = "disabled";
 248                                 };
 249
 250                                 ecspi1: ecspi@02008000 {
 251                                         #address-cells = <1>;
 252                                         #size-cells = <0>;
 253                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 254                                         reg = <0x02008000 0x4000>;
 255                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 256                                         clocks = <&clks IMX6UL_CLK_ECSPI1>,
 257                                                  <&clks IMX6UL_CLK_ECSPI1>;
 258                                         clock-names = "ipg", "per";
 259                                         dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
 260                                         dma-names = "rx", "tx";
 261                                         status = "disabled";
 262                                 };
 263
 264                                 ecspi2: ecspi@0200c000 {
 265                                         #address-cells = <1>;
 266                                         #size-cells = <0>;
 267                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 268                                         reg = <0x0200c000 0x4000>;
 269                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 270                                         clocks = <&clks IMX6UL_CLK_ECSPI2>,
 271                                                  <&clks IMX6UL_CLK_ECSPI2>;
 272                                         clock-names = "ipg", "per";
 273                                         dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
 274                                         dma-names = "rx", "tx";
 275                                         status = "disabled";
 276                                 };
 277
 278                                 ecspi3: ecspi@02010000 {
 279                                         #address-cells = <1>;
 280                                         #size-cells = <0>;
 281                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 282                                         reg = <0x02010000 0x4000>;
 283                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 284                                         clocks = <&clks IMX6UL_CLK_ECSPI3>,
 285                                                  <&clks IMX6UL_CLK_ECSPI3>;
 286                                         clock-names = "ipg", "per";
 287                                         dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
 288                                         dma-names = "rx", "tx";
 289                                         status = "disabled";
 290                                 };
 291
 292                                 ecspi4: ecspi@02014000 {
 293                                         #address-cells = <1>;
 294                                         #size-cells = <0>;
 295                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 296                                         reg = <0x02014000 0x4000>;
 297                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 298                                         clocks = <&clks IMX6UL_CLK_ECSPI4>,
 299                                                  <&clks IMX6UL_CLK_ECSPI4>;
 300                                         clock-names = "ipg", "per";
 301                                         dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
 302                                         dma-names = "rx", "tx";
 303                                         status = "disabled";
 304                                 };
 305
 306                                 uart7: serial@02018000 {
 307                                         compatible = "fsl,imx6ul-uart",
 308                                                      "fsl,imx6q-uart", "fsl,imx21-uart";
 309                                         reg = <0x02018000 0x4000>;
 310                                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 311                                         clocks = <&clks IMX6UL_CLK_UART7_IPG>,
 312                                                  <&clks IMX6UL_CLK_UART7_SERIAL>;
 313                                         clock-names = "ipg", "per";
 314                                         dmas = <&sdma 43 4 0>, <&sdma 44 4 0>;
 315                                         dma-names = "rx", "tx";
 316                                         status = "disabled";
 317                                 };
 318
 319                                 uart1: serial@02020000 {
 320                                         compatible = "fsl,imx6ul-uart",
 321                                                      "fsl,imx6q-uart", "fsl,imx21-uart";
 322                                         reg = <0x02020000 0x4000>;
 323                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 324                                         clocks = <&clks IMX6UL_CLK_UART1_IPG>,
 325                                                  <&clks IMX6UL_CLK_UART1_SERIAL>;
 326                                         clock-names = "ipg", "per";
 327                                         status = "disabled";
 328                                 };
 329
 330                                 esai: esai@02024000 {
 331                                         compatible = "fsl,imx6ull-esai";
 332                                         reg = <0x02024000 0x4000>;
 333                                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 334                                         clocks = <&clks IMX6UL_CLK_ESAI_IPG>,
 335                                                  <&clks IMX6UL_CLK_ESAI_MEM>,
 336                                                  <&clks IMX6UL_CLK_ESAI_EXTAL>,
 337                                                  <&clks IMX6UL_CLK_ESAI_IPG>,
 338                                                  <&clks IMX6UL_CLK_SPBA>;
 339                                         clock-names = "core", "mem", "extal",
 340                                                       "fsys", "dma";
 341                                         dmas = <&sdma 0 21 0>, <&sdma 47 21 0>;
 342                                         dma-names = "rx", "tx";
 343                                         dma-source = <&gpr 0 14 0 15>;
 344                                         status = "disabled";
 345                                 };
 346
 347                                 sai1: sai@02028000 {
 348                                         compatible = "fsl,imx6ul-sai",
 349                                                      "fsl,imx6sx-sai";
 350                                         reg = <0x02028000 0x4000>;
 351                                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 352                                         clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
 353                                                  <&clks IMX6UL_CLK_DUMMY>,
 354                                                  <&clks IMX6UL_CLK_SAI1>,
 355                                                  <&clks 0>, <&clks 0>;
 356                                         clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
 357                                         dma-names = "rx", "tx";
 358                                         dmas = <&sdma 35 24 0>, <&sdma 36 24 0>;
 359                                         status = "disabled";
 360                                 };
 361
 362                                 sai2: sai@0202c000 {
 363                                         compatible = "fsl,imx6ul-sai",
 364                                                      "fsl,imx6sx-sai";
 365                                         reg = <0x0202c000 0x4000>;
 366                                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 367                                         clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
 368                                                  <&clks IMX6UL_CLK_DUMMY>,
 369                                                  <&clks IMX6UL_CLK_SAI2>,
 370                                                  <&clks 0>, <&clks 0>;
 371                                         clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
 372                                         dma-names = "rx", "tx";
 373                                         dmas = <&sdma 37 24 0>, <&sdma 38 24 0>;
 374                                         status = "disabled";
 375                                 };
 376
 377                                 sai3: sai@02030000 {
 378                                         compatible = "fsl,imx6ul-sai",
 379                                                      "fsl,imx6sx-sai";
 380                                         reg = <0x02030000 0x4000>;
 381                                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 382                                         clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
 383                                                  <&clks IMX6UL_CLK_DUMMY>,
 384                                                  <&clks IMX6UL_CLK_SAI3>,
 385                                                  <&clks 0>, <&clks 0>;
 386                                         clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
 387                                         dma-names = "rx", "tx";
 388                                         dmas = <&sdma 39 24 0>, <&sdma 40 24 0>;
 389                                         status = "disabled";
 390                                 };
 391
 392                                 asrc: asrc@02034000 {
 393                                         compatible = "fsl,imx53-asrc";
 394                                         reg = <0x02034000 0x4000>;
 395                                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 396                                         clocks = <&clks IMX6UL_CLK_ASRC_IPG>,
 397                                                 <&clks IMX6UL_CLK_ASRC_MEM>, <&clks 0>,
 398                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 399                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 400                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 401                                                 <&clks IMX6UL_CLK_SPDIF>, <&clks 0>, <&clks 0>,
 402                                                 <&clks IMX6UL_CLK_SPBA>;
 403                                         clock-names = "mem", "ipg", "asrck_0",
 404                                                 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
 405                                                 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
 406                                                 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
 407                                                 "asrck_d", "asrck_e", "asrck_f", "dma";
 408                                         dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
 409                                                 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
 410                                         dma-names = "rxa", "rxb", "rxc",
 411                                                     "txa", "txb", "txc";
 412                                         fsl,asrc-rate  = <48000>;
 413                                         fsl,asrc-width = <16>;
 414                                         status = "okay";
 415                                 };
 416                         };
 417
 418                         tsc: tsc@02040000 {
 419                                 compatible = "fsl,imx6ul-tsc";
 420                                 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
 421                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 422                                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 423                                 clocks = <&clks IMX6UL_CLK_IPG>,
 424                                          <&clks IMX6UL_CLK_ADC2>;
 425                                 clock-names = "tsc", "adc";
 426                                 status = "disabled";
 427                         };
 428
 429                         pwm1: pwm@02080000 {
 430                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 431                                 reg = <0x02080000 0x4000>;
 432                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 433                                 clocks = <&clks IMX6UL_CLK_PWM1>,
 434                                          <&clks IMX6UL_CLK_PWM1>;
 435                                 clock-names = "ipg", "per";
 436                                 #pwm-cells = <2>;
 437                         };
 438
 439                         pwm2: pwm@02084000 {
 440                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 441                                 reg = <0x02084000 0x4000>;
 442                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 443                                 clocks = <&clks IMX6UL_CLK_DUMMY>,
 444                                          <&clks IMX6UL_CLK_DUMMY>;
 445                                 clock-names = "ipg", "per";
 446                                 #pwm-cells = <2>;
 447                         };
 448
 449                         pwm3: pwm@02088000 {
 450                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 451                                 reg = <0x02088000 0x4000>;
 452                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 453                                 clocks = <&clks IMX6UL_CLK_PWM3>,
 454                                          <&clks IMX6UL_CLK_PWM3>;
 455                                 clock-names = "ipg", "per";
 456                                 #pwm-cells = <2>;
 457                         };
 458
 459                         pwm4: pwm@0208c000 {
 460                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 461                                 reg = <0x0208c000 0x4000>;
 462                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 463                                 clocks = <&clks IMX6UL_CLK_DUMMY>,
 464                                          <&clks IMX6UL_CLK_DUMMY>;
 465                                 clock-names = "ipg", "per";
 466                                 #pwm-cells = <2>;
 467                         };
 468
 469                         flexcan1: can@02090000 {
 470                                 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
 471                                 reg = <0x02090000 0x4000>;
 472                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 473                                 clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
 474                                          <&clks IMX6UL_CLK_CAN1_SERIAL>;
 475                                 clock-names = "ipg", "per";
 476                                 stop-mode = <&gpr 0x10 1 0x10 17>;
 477                                 status = "disabled";
 478                         };
 479
 480                         flexcan2: can@02094000 {
 481                                 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
 482                                 reg = <0x02094000 0x4000>;
 483                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 484                                 clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
 485                                          <&clks IMX6UL_CLK_CAN2_SERIAL>;
 486                                 clock-names = "ipg", "per";
 487                                 stop-mode = <&gpr 0x10 2 0x10 18>;
 488                                 status = "disabled";
 489                         };
 490
 491                         gpt1: gpt@02098000 {
 492                                 compatible = "fsl,imx6ul-gpt", "fsl,imx31-gpt";
 493                                 reg = <0x02098000 0x4000>;
 494                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 495                                 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
 496                                          <&clks IMX6UL_CLK_GPT1_SERIAL>;
 497                                 clock-names = "ipg", "per";
 498                         };
 499
 500                         gpio1: gpio@0209c000 {
 501                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 502                                 reg = <0x0209c000 0x4000>;
 503                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 504                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 505                                 gpio-controller;
 506                                 #gpio-cells = <2>;
 507                                 interrupt-controller;
 508                                 #interrupt-cells = <2>;
 509                         };
 510
 511                         gpio2: gpio@020a0000 {
 512                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 513                                 reg = <0x020a0000 0x4000>;
 514                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 515                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 516                                 gpio-controller;
 517                                 #gpio-cells = <2>;
 518                                 interrupt-controller;
 519                                 #interrupt-cells = <2>;
 520                         };
 521
 522                         gpio3: gpio@020a4000 {
 523                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 524                                 reg = <0x020a4000 0x4000>;
 525                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 526                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 527                                 gpio-controller;
 528                                 #gpio-cells = <2>;
 529                                 interrupt-controller;
 530                                 #interrupt-cells = <2>;
 531                         };
 532
 533                         gpio4: gpio@020a8000 {
 534                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 535                                 reg = <0x020a8000 0x4000>;
 536                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 537                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 538                                 gpio-controller;
 539                                 #gpio-cells = <2>;
 540                                 interrupt-controller;
 541                                 #interrupt-cells = <2>;
 542                         };
 543
 544                         gpio5: gpio@020ac000 {
 545                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 546                                 reg = <0x020ac000 0x4000>;
 547                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 548                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 549                                 gpio-controller;
 550                                 #gpio-cells = <2>;
 551                                 interrupt-controller;
 552                                 #interrupt-cells = <2>;
 553                         };
 554
 555                         snvslp: snvs@020b0000 {
 556                                 compatible = "fsl,imx6ul-snvs";
 557                                 reg = <0x020b0000 0x4000>;
 558                                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 559                         };
 560
 561                         fec2: ethernet@020b4000 {
 562                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
 563                                 reg = <0x020b4000 0x4000>;
 564                                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 565                                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 566                                 clocks = <&clks IMX6UL_CLK_ENET>,
 567                                          <&clks IMX6UL_CLK_ENET_AHB>,
 568                                          <&clks IMX6UL_CLK_ENET_PTP>,
 569                                          <&clks IMX6UL_CLK_ENET2_REF_125M>,
 570                                          <&clks IMX6UL_CLK_ENET2_REF_125M>;
 571                                 clock-names = "ipg", "ahb", "ptp",
 572                                               "enet_clk_ref", "enet_out";
 573                                 stop-mode = <&gpr 0x10 4>;
 574                                 fsl,num-tx-queues=<1>;
 575                                 fsl,num-rx-queues=<1>;
 576                                 fsl,magic-packet;
 577                                 fsl,wakeup_irq = <0>;
 578                                 status = "disabled";
 579                         };
 580
 581                         kpp: kpp@020b8000 {
 582                                 compatible = "fsl,imx6ul-kpp", "fsl,imx21-kpp";
 583                                 reg = <0x020b8000 0x4000>;
 584                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 585                                 clocks = <&clks IMX6UL_CLK_DUMMY>;
 586                                 status = "disabled";
 587                         };
 588
 589                         wdog1: wdog@020bc000 {
 590                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 591                                 reg = <0x020bc000 0x4000>;
 592                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 593                                 clocks = <&clks IMX6UL_CLK_WDOG1>;
 594                         };
 595
 596                         wdog2: wdog@020c0000 {
 597                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 598                                 reg = <0x020c0000 0x4000>;
 599                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 600                                 clocks = <&clks IMX6UL_CLK_WDOG2>;
 601                                 status = "disabled";
 602                         };
 603
 604                         clks: ccm@020c4000 {
 605                                 compatible = "fsl,imx6ul-ccm";
 606                                 reg = <0x020c4000 0x4000>;
 607                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 608                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 609                                 #clock-cells = <1>;
 610                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
 611                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
 612                         };
 613
 614                         anatop: anatop@020c8000 {
 615                                 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
 616                                              "syscon", "simple-bus";
 617                                 reg = <0x020c8000 0x1000>;
 618                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 619                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 620                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 621
 622                                 reg_3p0: regulator-3p0@120 {
 623                                         compatible = "fsl,anatop-regulator";
 624                                         regulator-name = "vdd3p0";
 625                                         regulator-min-microvolt = <2625000>;
 626                                         regulator-max-microvolt = <3400000>;
 627                                         anatop-reg-offset = <0x120>;
 628                                         anatop-vol-bit-shift = <8>;
 629                                         anatop-vol-bit-width = <5>;
 630                                         anatop-min-bit-val = <0>;
 631                                         anatop-min-voltage = <2625000>;
 632                                         anatop-max-voltage = <3400000>;
 633                                         anatop-enable-bit = <0>;
 634                                 };
 635
 636                                 reg_arm: regulator-vddcore@140 {
 637                                         compatible = "fsl,anatop-regulator";
 638                                         regulator-name = "cpu";
 639                                         regulator-min-microvolt = <725000>;
 640                                         regulator-max-microvolt = <1450000>;
 641                                         regulator-always-on;
 642                                         anatop-reg-offset = <0x140>;
 643                                         anatop-vol-bit-shift = <0>;
 644                                         anatop-vol-bit-width = <5>;
 645                                         anatop-delay-reg-offset = <0x170>;
 646                                         anatop-delay-bit-shift = <24>;
 647                                         anatop-delay-bit-width = <2>;
 648                                         anatop-min-bit-val = <1>;
 649                                         anatop-min-voltage = <725000>;
 650                                         anatop-max-voltage = <1450000>;
 651                                 };
 652
 653                                 reg_soc: regulator-vddsoc@140 {
 654                                         compatible = "fsl,anatop-regulator";
 655                                         regulator-name = "vddsoc";
 656                                         regulator-min-microvolt = <725000>;
 657                                         regulator-max-microvolt = <1450000>;
 658                                         regulator-always-on;
 659                                         anatop-reg-offset = <0x140>;
 660                                         anatop-vol-bit-shift = <18>;
 661                                         anatop-vol-bit-width = <5>;
 662                                         anatop-delay-reg-offset = <0x170>;
 663                                         anatop-delay-bit-shift = <28>;
 664                                         anatop-delay-bit-width = <2>;
 665                                         anatop-min-bit-val = <1>;
 666                                         anatop-min-voltage = <725000>;
 667                                         anatop-max-voltage = <1450000>;
 668                                 };
 669                         };
 670
 671                         usbphy1: usbphy@020c9000 {
 672                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
 673                                 reg = <0x020c9000 0x1000>;
 674                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 675                                 clocks = <&clks IMX6UL_CLK_USBPHY1>;
 676                                 phy-3p0-supply = <&reg_3p0>;
 677                                 fsl,anatop = <&anatop>;
 678                         };
 679
 680                         usbphy2: usbphy@020ca000 {
 681                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
 682                                 reg = <0x020ca000 0x1000>;
 683                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 684                                 clocks = <&clks IMX6UL_CLK_USBPHY2>;
 685                                 phy-3p0-supply = <&reg_3p0>;
 686                                 fsl,anatop = <&anatop>;
 687                         };
 688
 689                         tempmon: tempmon {
 690                                 compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
 691                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 692                                 fsl,tempmon = <&anatop>;
 693                                 fsl,tempmon-data = <&ocotp>;
 694                                 clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
 695                         };
 696
 697                         snvs: snvs@020cc000 {
 698                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 699                                 reg = <0x020cc000 0x4000>;
 700
 701                                 snvs_rtc: snvs-rtc-lp {
 702                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 703                                         regmap = <&snvs>;
 704                                         offset = <0x34>;
 705                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 706                                 };
 707
 708                                 snvs_poweroff: snvs-poweroff {
 709                                         compatible = "syscon-poweroff";
 710                                         regmap = <&snvs>;
 711                                         offset = <0x38>;
 712                                         mask = <0x61>;
 713                                 };
 714
 715                                 snvs_pwrkey: snvs-powerkey {
 716                                         compatible = "fsl,sec-v4.0-pwrkey";
 717                                         regmap = <&snvs>;
 718                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 719                                         linux,keycode = <KEY_POWER>;
 720                                         wakeup;
 721                                 };
 722                         };
 723
 724                         epit1: epit@020d0000 {
 725                                 reg = <0x020d0000 0x4000>;
 726                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 727                         };
 728
 729                         epit2: epit@020d4000 {
 730                                 reg = <0x020d4000 0x4000>;
 731                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 732                         };
 733
 734                         src: src@020d8000 {
 735                                 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
 736                                 reg = <0x020d8000 0x4000>;
 737                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 738                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 739                                 #reset-cells = <1>;
 740                         };
 741
 742                         gpc: gpc@020dc000 {
 743                                 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
 744                                 reg = <0x020dc000 0x4000>;
 745                                 interrupt-controller;
 746                                 #interrupt-cells = <3>;
 747                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 748                                 interrupt-parent = <&intc>;
 749                                 fsl,mf-mix-wakeup-irq = <0xfc00000 0x7d00 0x0 0x1400640>;
 750                         };
 751
 752                         iomuxc: iomuxc@020e0000 {
 753                                 compatible = "fsl,imx6ul-iomuxc";
 754                                 reg = <0x020e0000 0x4000>;
 755                         };
 756
 757                         gpr: iomuxc-gpr@020e4000 {
 758                                 compatible = "fsl,imx6ul-iomuxc-gpr", "syscon";
 759                                 reg = <0x020e4000 0x4000>;
 760                         };
 761
 762                         mqs: mqs {
 763                                 compatible = "fsl,imx6sx-mqs";
 764                                 gpr = <&gpr>;
 765                                 status = "disabled";
 766                         };
 767
 768                         gpt2: gpt@020e8000 {
 769                                 compatible = "fsl,imx6ul-gpt", "fsl,imx31-gpt";
 770                                 reg = <0x020e8000 0x4000>;
 771                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 772                                 clocks = <&clks IMX6UL_CLK_DUMMY>,
 773                                          <&clks IMX6UL_CLK_DUMMY>;
 774                                 clock-names = "ipg", "per";
 775                         };
 776
 777                         sdma: sdma@020ec000 {
 778                                 compatible = "fsl,imx6ul-sdma", "fsl,imx35-sdma";
 779                                 reg = <0x020ec000 0x4000>;
 780                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 781                                 clocks = <&clks IMX6UL_CLK_SDMA>,
 782                                          <&clks IMX6UL_CLK_SDMA>;
 783                                 clock-names = "ipg", "ahb";
 784                                 #dma-cells = <3>;
 785                                 iram = <&ocram>;
 786                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 787                         };
 788
 789                         pwm5: pwm@020f0000 {
 790                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 791                                 reg = <0x020f0000 0x4000>;
 792                                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 793                                 clocks = <&clks IMX6UL_CLK_DUMMY>,
 794                                          <&clks IMX6UL_CLK_DUMMY>;
 795                                 clock-names = "ipg", "per";
 796                                 #pwm-cells = <2>;
 797                         };
 798
 799                         pwm6: pwm@020f4000 {
 800                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 801                                 reg = <0x020f4000 0x4000>;
 802                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 803                                 clocks = <&clks IMX6UL_CLK_DUMMY>,
 804                                          <&clks IMX6UL_CLK_DUMMY>;
 805                                 clock-names = "ipg", "per";
 806                                 #pwm-cells = <2>;
 807                         };
 808
 809                         pwm7: pwm@020f8000 {
 810                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 811                                 reg = <0x020f8000 0x4000>;
 812                                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 813                                 clocks = <&clks IMX6UL_CLK_DUMMY>,
 814                                          <&clks IMX6UL_CLK_DUMMY>;
 815                                 clock-names = "ipg", "per";
 816                                 #pwm-cells = <2>;
 817                         };
 818
 819                         pwm8: pwm@020fc000 {
 820                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 821                                 reg = <0x020fc000 0x4000>;
 822                                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 823                                 clocks = <&clks IMX6UL_CLK_DUMMY>,
 824                                          <&clks IMX6UL_CLK_DUMMY>;
 825                                 clock-names = "ipg", "per";
 826                                 #pwm-cells = <2>;
 827                         };
 828                 };
 829
 830                 aips2: aips-bus@02100000 {
 831                         compatible = "fsl,aips-bus", "simple-bus";
 832                         #address-cells = <1>;
 833                         #size-cells = <1>;
 834                         reg = <0x02100000 0x100000>;
 835                         ranges;
 836
 837                         usbotg1: usb@02184000 {
 838                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
 839                                 reg = <0x02184000 0x200>;
 840                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 841                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
 842                                 fsl,usbphy = <&usbphy1>;
 843                                 fsl,usbmisc = <&usbmisc 0>;
 844                                 fsl,anatop = <&anatop>;
 845                                 ahb-burst-config = <0x0>;
 846                                 tx-burst-size-dword = <0x10>;
 847                                 rx-burst-size-dword = <0x10>;
 848                                 status = "disabled";
 849                         };
 850
 851                         usbotg2: usb@02184200 {
 852                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
 853                                 reg = <0x02184200 0x200>;
 854                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 855                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
 856                                 fsl,usbphy = <&usbphy2>;
 857                                 fsl,usbmisc = <&usbmisc 1>;
 858                                 ahb-burst-config = <0x0>;
 859                                 tx-burst-size-dword = <0x10>;
 860                                 rx-burst-size-dword = <0x10>;
 861                                 status = "disabled";
 862                         };
 863
 864                         usbmisc: usbmisc@02184800 {
 865                                 #index-cells = <1>;
 866                                 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
 867                                 reg = <0x02184800 0x200>;
 868                         };
 869
 870                         fec1: ethernet@02188000 {
 871                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
 872                                 reg = <0x02188000 0x4000>;
 873                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 874                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 875                                 clocks = <&clks IMX6UL_CLK_ENET>,
 876                                          <&clks IMX6UL_CLK_ENET_AHB>,
 877                                          <&clks IMX6UL_CLK_ENET_PTP>,
 878                                          <&clks IMX6UL_CLK_ENET_REF>,
 879                                          <&clks IMX6UL_CLK_ENET_REF>;
 880                                 clock-names = "ipg", "ahb", "ptp",
 881                                               "enet_clk_ref", "enet_out";
 882                                 stop-mode = <&gpr 0x10 3>;
 883                                 fsl,num-tx-queues=<1>;
 884                                 fsl,num-rx-queues=<1>;
 885                                 fsl,magic-packet;
 886                                 fsl,wakeup_irq = <0>;
 887                                 status = "disabled";
 888                         };
 889
 890                         usdhc1: usdhc@02190000 {
 891                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 892                                 reg = <0x02190000 0x4000>;
 893                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 894                                 clocks = <&clks IMX6UL_CLK_USDHC1>,
 895                                          <&clks IMX6UL_CLK_USDHC1>,
 896                                          <&clks IMX6UL_CLK_USDHC1>;
 897                                 clock-names = "ipg", "ahb", "per";
 898                                 bus-width = <4>;
 899                                 fsl,tuning-step= <2>;
 900                                 status = "disabled";
 901                         };
 902
 903                         usdhc2: usdhc@02194000 {
 904                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 905                                 reg = <0x02194000 0x4000>;
 906                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 907                                 clocks = <&clks IMX6UL_CLK_USDHC2>,
 908                                          <&clks IMX6UL_CLK_USDHC2>,
 909                                          <&clks IMX6UL_CLK_USDHC2>;
 910                                 clock-names = "ipg", "ahb", "per";
 911                                 bus-width = <4>;
 912                                 fsl,tuning-step= <2>;
 913                                 status = "disabled";
 914                         };
 915
 916                         adc1: adc@02198000 {
 917                                 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
 918                                 reg = <0x02198000 0x4000>;
 919                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 920                                 clocks = <&clks IMX6UL_CLK_ADC1>;
 921                                 num-channels = <2>;
 922                                 clock-names = "adc";
 923                                 status = "disabled";
 924                         };
 925
 926                         i2c1: i2c@021a0000 {
 927                                 #address-cells = <1>;
 928                                 #size-cells = <0>;
 929                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 930                                 reg = <0x021a0000 0x4000>;
 931                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 932                                 clocks = <&clks IMX6UL_CLK_I2C1>;
 933                                 status = "disabled";
 934                         };
 935
 936                         i2c2: i2c@021a4000 {
 937                                 #address-cells = <1>;
 938                                 #size-cells = <0>;
 939                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 940                                 reg = <0x021a4000 0x4000>;
 941                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 942                                 clocks = <&clks IMX6UL_CLK_I2C2>;
 943                                 status = "disabled";
 944                         };
 945
 946                         i2c3: i2c@021a8000 {
 947                                 #address-cells = <1>;
 948                                 #size-cells = <0>;
 949                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 950                                 reg = <0x021a8000 0x4000>;
 951                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 952                                 clocks = <&clks IMX6UL_CLK_I2C3>;
 953                                 status = "disabled";
 954                         };
 955
 956                         romcp@021ac000 {
 957                                 compatible = "fsl,imx6ul-romcp", "syscon";
 958                                 reg = <0x021ac000 0x4000>;
 959                         };
 960
 961                         mmdc: mmdc@021b0000 {
 962                                 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
 963                                 reg = <0x021b0000 0x4000>;
 964                         };
 965
 966                         weim: weim@021b8000 {
 967                                 compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim";
 968                                 reg = <0x021b8000 0x4000>;
 969                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 970                                 clocks = <&clks IMX6UL_CLK_DUMMY>;
 971                         };
 972
 973                         ocotp: ocotp-ctrl@021bc000 {
 974                                 compatible = "fsl,imx6ull-ocotp", "syscon";
 975                                 reg = <0x021bc000 0x4000>;
 976                                 clocks = <&clks IMX6UL_CLK_OCOTP>;
 977                         };
 978
 979                         csu: csu@021c0000 {
 980                                 compatible = "fsl,imx6ul-csu";
 981                                 reg = <0x021c0000 0x4000>;
 982                                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 983                                 status = "disabled";
 984                         };
 985
 986                         csi: csi@021c4000 {
 987                                 compatible = "fsl,imx6ul-csi", "fsl,imx6s-csi";
 988                                 reg = <0x021c4000 0x4000>;
 989                                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 990                                 clocks = <&clks IMX6UL_CLK_DUMMY>,
 991                                         <&clks IMX6UL_CLK_CSI>,
 992                                         <&clks IMX6UL_CLK_DUMMY>;
 993                                 clock-names = "disp-axi", "csi_mclk", "disp_dcic";
 994                                 status = "disabled";
 995                         };
 996
 997                         lcdif: lcdif@021c8000 {
 998                                 compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
 999                                 reg = <0x021c8000 0x4000>;
1000                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1001                                 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
1002                                          <&clks IMX6UL_CLK_LCDIF_APB>,
1003                                          <&clks IMX6UL_CLK_DUMMY>;
1004                                 clock-names = "pix", "axi", "disp_axi";
1005                                 status = "disabled";
1006                         };
1007
1008                         pxp: pxp@021cc000 {
1009                                 compatible = "fsl,imx6ull-pxp-dma", "fsl,imx7d-pxp-dma";
1010                                 reg = <0x021cc000 0x4000>;
1011                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1012                                         <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1013                                 clocks = <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_PXP>;
1014                                 clock-names = "pxp_ipg", "pxp_axi";
1015                                 status = "disabled";
1016                         };
1017
1018                         qspi: qspi@021e0000 {
1019                                 #address-cells = <1>;
1020                                 #size-cells = <0>;
1021                                 compatible = "fsl,imx6ull-qspi", "fsl,imx6ul-qspi";
1022                                 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1023                                 reg-names = "QuadSPI", "QuadSPI-memory";
1024                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1025                                 clocks = <&clks IMX6UL_CLK_QSPI>,
1026                                          <&clks IMX6UL_CLK_QSPI>;
1027                                 clock-names = "qspi_en", "qspi";
1028                                 status = "disabled";
1029                         };
1030
1031                         wdog3: wdog@021e4000 {
1032                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
1033                                 reg = <0x021e4000 0x4000>;
1034                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1035                                 clocks = <&clks IMX6UL_CLK_WDOG3>;
1036                                 status = "disabled";
1037                         };
1038
1039                         uart2: serial@021e8000 {
1040                                 compatible = "fsl,imx6ul-uart",
1041                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1042                                 reg = <0x021e8000 0x4000>;
1043                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1044                                 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
1045                                          <&clks IMX6UL_CLK_UART2_SERIAL>;
1046                                 clock-names = "ipg", "per";
1047                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1048                                 dma-names = "rx", "tx";
1049                                 status = "disabled";
1050                         };
1051
1052                         uart3: serial@021ec000 {
1053                                 compatible = "fsl,imx6ul-uart",
1054                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1055                                 reg = <0x021ec000 0x4000>;
1056                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1057                                 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
1058                                          <&clks IMX6UL_CLK_UART3_SERIAL>;
1059                                 clock-names = "ipg", "per";
1060                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1061                                 dma-names = "rx", "tx";
1062                                 status = "disabled";
1063                         };
1064
1065                         uart4: serial@021f0000 {
1066                                 compatible = "fsl,imx6ul-uart",
1067                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1068                                 reg = <0x021f0000 0x4000>;
1069                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1070                                 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
1071                                          <&clks IMX6UL_CLK_UART4_SERIAL>;
1072                                 clock-names = "ipg", "per";
1073                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1074                                 dma-names = "rx", "tx";
1075                                 status = "disabled";
1076                         };
1077
1078                         uart5: serial@021f4000 {
1079                                 compatible = "fsl,imx6ul-uart",
1080                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1081                                 reg = <0x021f4000 0x4000>;
1082                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1083                                 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
1084                                          <&clks IMX6UL_CLK_UART5_SERIAL>;
1085                                 clock-names = "ipg", "per";
1086                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1087                                 dma-names = "rx", "tx";
1088                                 status = "disabled";
1089                         };
1090
1091                         i2c4: i2c@021f8000 {
1092                                 #address-cells = <1>;
1093                                 #size-cells = <0>;
1094                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
1095                                 reg = <0x021f8000 0x4000>;
1096                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1097                                 clocks = <&clks IMX6UL_CLK_I2C4>;
1098                                 status = "disabled";
1099                         };
1100
1101                         uart6: serial@021fc000 {
1102                                 compatible = "fsl,imx6ul-uart",
1103                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1104                                 reg = <0x021fc000 0x4000>;
1105                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1106                                 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
1107                                          <&clks IMX6UL_CLK_UART6_SERIAL>;
1108                                 clock-names = "ipg", "per";
1109                                 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1110                                 dma-names = "rx", "tx";
1111                                 status = "disabled";
1112                         };
1113                 };
1114
1115                 aips3: aips-bus@02200000 {
1116                         compatible = "fsl,aips-bus", "simple-bus";
1117                         #address-cells = <1>;
1118                         #size-cells = <1>;
1119                         reg = <0x02200000 0x100000>;
1120                         ranges;
1121
1122                         dcp: dcp@02280000 {
1123                                 reg = <0x02280000 0x4000>;
1124                                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1125                                              <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1126                                              <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1127                                 /*clocks = <&clks IMX6UL_CLK_DCP>;*/
1128                                 clock-names = "dcp";
1129                                 status = "disabled";
1130                         };
1131
1132                         rngb: rngb@02284000 {
1133                                 reg = <0x02284000 0x4000>;
1134                                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1135                         };
1136
1137                         uart8: serial@02288000 {
1138                                 compatible = "fsl,imx6ul-uart",
1139                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1140                                 reg = <0x02288000 0x4000>;
1141                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1142                                 clocks = <&clks IMX6UL_CLK_UART8_IPG>,
1143                                          <&clks IMX6UL_CLK_UART8_SERIAL>;
1144                                 clock-names = "ipg", "per";
1145                                 dmas = <&sdma 45 4 0>, <&sdma 46 4 0>;
1146                                 dma-names = "rx", "tx";
1147                                 status = "disabled";
1148                         };
1149
1150                         epdc: epdc@0228c000 {
1151                                 compatible = "fsl,imx7d-epdc";
1152                                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1153                                 reg = <0x0228c000 0x4000>;
1154                                 clocks = <&clks IMX6UL_CLK_EPDC_ACLK>,
1155                                          <&clks IMX6UL_CLK_EPDC_PIX>;
1156                                 clock-names = "epdc_axi", "epdc_pix";
1157                                 /* Need to fix epdc-ram */
1158                                 /* epdc-ram = <&gpr 0x4 30>; */
1159                                 status = "disabled";
1160                         };
1161
1162                         iomuxc_snvs: iomuxc-snvs@02290000 {
1163                                 compatible = "fsl,imx6ull-iomuxc-snvs";
1164                                 reg = <0x02290000 0x10000>;
1165                         };
1166
1167                         snvs_gpr: snvs-gpr@0x02294000 {
1168                                 compatible = "fsl, imx6ull-snvs-gpr";
1169                                 reg = <0x02294000 0x10000>;
1170                         };
1171                 };
1172         };
1173 };