1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2018-2019 Toradex AG
7 #include <dt-bindings/gpio/gpio.h>
8 #include "imx6ull.dtsi"
11 model = "Toradex Colibri iMX6ULL";
12 compatible = "toradex,imx6ull-colibri", "fsl,imx6ull";
16 usb0 = &usbotg1; /* required for ums */
23 reg_module_3v3: regulator-module-3v3 {
24 compatible = "regulator-fixed";
26 regulator-name = "+V3.3";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
31 reg_module_3v3_avdd: regulator-module-3v3-avdd {
32 compatible = "regulator-fixed";
34 regulator-name = "+V3.3_AVDD_AUDIO";
35 regulator-min-microvolt = <3300000>;
36 regulator-max-microvolt = <3300000>;
39 reg_5v0: regulator-5v0 {
40 compatible = "regulator-fixed";
41 regulator-name = "5V";
42 regulator-min-microvolt = <5000000>;
43 regulator-max-microvolt = <5000000>;
46 reg_sd1_vmmc: regulator-sd1-vmmc {
47 compatible = "regulator-gpio";
48 gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_snvs_reg_sd>;
52 regulator-name = "+V3.3_1.8_SD";
53 regulator-min-microvolt = <1800000>;
54 regulator-max-microvolt = <3300000>;
55 states = <1800000 0x1 3300000 0x0>;
56 vin-supply = <®_module_3v3>;
59 reg_usbh_vbus: regulator-usbh-vbus {
60 compatible = "regulator-fixed";
61 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_usbh_reg>;
63 regulator-name = "VCC_USB[1-4]";
64 regulator-min-microvolt = <5000000>;
65 regulator-max-microvolt = <5000000>;
66 gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; /* USBH_PEN */
67 vin-supply = <®_5v0>;
73 vref-supply = <®_module_3v3_avdd>;
78 cs-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>;
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
85 pinctrl-names = "default";
86 pinctrl-0 = <&pinctrl_enet2>;
88 phy-handle = <ðphy1>;
95 ethphy1: ethernet-phy@2 {
96 compatible = "ethernet-phy-ieee802.3-c22";
104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_gpmi_nand>;
107 nand-ecc-mode = "hw";
108 nand-ecc-strength = <8>;
109 nand-ecc-step-size = <512>;
114 pinctrl-names = "default", "gpio";
115 pinctrl-0 = <&pinctrl_i2c1>;
116 pinctrl-1 = <&pinctrl_i2c1_gpio>;
117 sda-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
118 scl-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
123 pinctrl-names = "default", "gpio";
124 pinctrl-0 = <&pinctrl_i2c2>;
125 pinctrl-1 = <&pinctrl_i2c2_gpio>;
126 sda-gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
127 scl-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
131 compatible = "adi,ad7879-1";
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_snvs_ad7879_int>;
135 interrupt-parent = <&gpio5>;
136 interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
137 touchscreen-max-pressure = <4096>;
138 adi,resistance-plate-x = <120>;
139 adi,first-conversion-delay = /bits/ 8 <3>;
140 adi,acquisition-time = /bits/ 8 <1>;
141 adi,median-filter-size = /bits/ 8 <2>;
142 adi,averaging = /bits/ 8 <1>;
143 adi,conversion-interval = /bits/ 8 <255>;
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_lcdif_dat
150 &pinctrl_lcdif_ctrl>;
154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_pwm4>;
160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_pwm5>;
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_pwm6>;
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_pwm7>;
187 pinctrl-names = "default";
188 pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_uart2>;
204 pinctrl-names = "default";
205 pinctrl-0 = <&pinctrl_uart5>;
221 vbus-supply = <®_usbh_vbus>;
227 assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
228 assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
229 assigned-clock-rates = <0>, <198000000>;
230 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */
231 pinctrl-names = "default", "state_100mhz", "state_200mhz";
232 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
233 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
234 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
235 vmmc-supply = <®_sd1_vmmc>;
240 pinctrl_enet2: enet2-grp {
242 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
243 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
244 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
245 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
246 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
247 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
248 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
249 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
250 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
251 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
255 pinctrl_gpio1: gpio1-grp {
257 MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x74 /* SODIMM 55 */
258 MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x74 /* SODIMM 63 */
259 MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0X14 /* SODIMM 77 */
260 MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x14 /* SODIMM 99 */
261 MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x14 /* SODIMM 133 */
262 MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x14 /* SODIMM 135 */
263 MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x14 /* SODIMM 100 */
264 MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x14 /* SODIMM 102 */
265 MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x14 /* SODIMM 104 */
266 MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x14 /* SODIMM 186 */
270 pinctrl_gpio2: gpio2-grp { /* Camera */
272 MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x74 /* SODIMM 69 */
273 MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x14 /* SODIMM 75 */
274 MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x14 /* SODIMM 85 */
275 MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x14 /* SODIMM 96 */
276 MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x14 /* SODIMM 98 */
280 pinctrl_gpio3: gpio3-grp { /* CAN2 */
282 MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x14 /* SODIMM 178 */
283 MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x14 /* SODIMM 188 */
287 pinctrl_gpio4: gpio4-grp {
289 MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x74 /* SODIMM 65 */
293 pinctrl_gpio5: gpio5-grp { /* ATMEL MXT TOUCH */
295 MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x74 /* SODIMM 106 */
299 pinctrl_gpio6: gpio6-grp { /* Wifi pins */
301 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x14 /* SODIMM 89 */
302 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x14 /* SODIMM 79 */
303 MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x14 /* SODIMM 81 */
304 MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x14 /* SODIMM 97 */
305 MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x14 /* SODIMM 101 */
306 MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x14 /* SODIMM 103 */
307 MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x14 /* SODIMM 94 */
311 pinctrl_can_int: canint-grp {
313 MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0X14 /* SODIMM 73 */
317 pinctrl_ecspi1_cs: ecspi1-cs-grp {
319 MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x000a0
323 pinctrl_ecspi1: ecspi1-grp {
325 MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0
326 MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0
327 MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0
331 pinctrl_flexcan2: flexcan2-grp {
333 MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020
334 MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020
338 pinctrl_gpio_bl_on: gpio-bl-on-grp {
340 MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x000a0
344 pinctrl_gpmi_nand: gpmi-nand-grp {
346 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9
347 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9
348 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x100a9
349 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x100a9
350 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x100a9
351 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x100a9
352 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x100a9
353 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x100a9
354 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x100a9
355 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x100a9
356 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x100a9
357 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x100a9
358 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x100a9
359 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9
363 pinctrl_i2c1: i2c1-grp {
365 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
366 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
370 pinctrl_i2c1_gpio: i2c1-gpio-grp {
372 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0
373 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0
377 pinctrl_i2c2: i2c2-grp {
379 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
380 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
384 pinctrl_i2c2_gpio: i2c2-gpio-grp {
386 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0
387 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0
391 pinctrl_lcdif_dat: lcdif-dat-grp {
393 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079
394 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079
395 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x00079
396 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x00079
397 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x00079
398 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x00079
399 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x00079
400 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x00079
401 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x00079
402 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x00079
403 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x00079
404 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x00079
405 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x00079
406 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x00079
407 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x00079
408 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x00079
409 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x00079
410 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079
414 pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
416 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079
417 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079
418 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x00079
419 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x00079
423 pinctrl_pwm4: pwm4-grp {
425 MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079
429 pinctrl_pwm5: pwm5-grp {
431 MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079
435 pinctrl_pwm6: pwm6-grp {
437 MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079
441 pinctrl_pwm7: pwm7-grp {
443 MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079
447 pinctrl_uart1: uart1-grp {
449 MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1
450 MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1
451 MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x1b0b1
452 MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1
456 pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */
458 MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x1b0b1 /* DCD */
459 MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x1b0b1 /* DSR */
460 MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x1b0b1 /* DTR */
461 MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x1b0b1 /* RI */
465 pinctrl_uart2: uart2-grp {
467 MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1
468 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1
469 MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1
470 MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1
473 pinctrl_uart5: uart5-grp {
475 MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1
476 MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1
480 pinctrl_usbh_reg: gpio-usbh-reg {
482 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x1b0b1 /* SODIMM 129 USBH PEN */
486 pinctrl_usdhc1: usdhc1-grp {
488 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059
489 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x10059
490 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
491 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
492 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
493 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
497 pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
499 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170b9
500 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100b9
501 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
502 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
503 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
504 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
508 pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
510 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170f9
511 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100f9
512 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
513 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
514 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
515 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
519 pinctrl_usdhc2: usdhc2-grp {
521 MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059
522 MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059
523 MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059
524 MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059
525 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059
526 MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17059
528 MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x14
534 pinctrl_snvs_gpio1: snvs-gpio1-grp {
536 MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x14 /* SODIMM 93 */
537 MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x14 /* SODIMM 95 */
538 MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x74 /* SODIMM 105 */
539 MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x14 /* SODIMM 131 USBH OC */
540 MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x74 /* SODIMM 138 */
544 pinctrl_snvs_gpio2: snvs-gpio2-grp { /* ATMEL MXT TOUCH */
546 MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x74 /* SODIMM 107 */
550 pinctrl_snvs_gpio3: snvs-gpio3-grp { /* Wifi pins */
552 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x14 /* SODIMM 127 */
556 pinctrl_snvs_ad7879_int: snvs-ad7879-int { /* TOUCH Interrupt */
558 MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0
562 pinctrl_snvs_reg_sd: snvs-reg-sd-grp {
564 MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x4001b8b0
568 pinctrl_snvs_usbc_det: snvs-usbc-det-grp {
570 MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0
574 pinctrl_snvs_gpiokeys: snvs-gpiokeys-grp {
576 MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130b0
580 pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp {
582 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* CD */
586 pinctrl_snvs_wifi_pdn: snvs-wifi-pdn-grp {
588 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x14