arch/arm/dts/imx6ull-colibri.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2018-2019 Toradex AG
   4  */
   5
   6 /dts-v1/;
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include "imx6ull.dtsi"
   9
  10 / {
  11         model = "Toradex Colibri iMX6ULL";
  12         compatible = "toradex,colibri-imx6ull", "fsl,imx6ull";
  13
  14         aliases {
  15                 mmc0 = &usdhc1;
  16                 usb0 = &usbotg1; /* required for ums */
  17         };
  18
  19         chosen {
  20                 stdout-path = &uart1;
  21         };
  22
  23         reg_module_3v3: regulator-module-3v3 {
  24                 compatible = "regulator-fixed";
  25                 regulator-always-on;
  26                 regulator-name = "+V3.3";
  27                 regulator-min-microvolt = <3300000>;
  28                 regulator-max-microvolt = <3300000>;
  29         };
  30
  31         reg_module_3v3_avdd: regulator-module-3v3-avdd {
  32                 compatible = "regulator-fixed";
  33                 regulator-always-on;
  34                 regulator-name = "+V3.3_AVDD_AUDIO";
  35                 regulator-min-microvolt = <3300000>;
  36                 regulator-max-microvolt = <3300000>;
  37         };
  38
  39         reg_5v0: regulator-5v0 {
  40                 compatible = "regulator-fixed";
  41                 regulator-name = "5V";
  42                 regulator-min-microvolt = <5000000>;
  43                 regulator-max-microvolt = <5000000>;
  44         };
  45
  46         reg_sd1_vmmc: regulator-sd1-vmmc {
  47                 compatible = "regulator-gpio";
  48                 gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
  49                 pinctrl-names = "default";
  50                 pinctrl-0 = <&pinctrl_snvs_reg_sd>;
  51                 regulator-always-on;
  52                 regulator-name = "+V3.3_1.8_SD";
  53                 regulator-min-microvolt = <1800000>;
  54                 regulator-max-microvolt = <3300000>;
  55                 states = <1800000 0x1 3300000 0x0>;
  56                 vin-supply = <&reg_module_3v3>;
  57         };
  58
  59         reg_usbh_vbus: regulator-usbh-vbus {
  60                 compatible = "regulator-fixed";
  61                 pinctrl-names = "default";
  62                 pinctrl-0 = <&pinctrl_usbh_reg>;
  63                 regulator-name = "VCC_USB[1-4]";
  64                 regulator-min-microvolt = <5000000>;
  65                 regulator-max-microvolt = <5000000>;
  66                 gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; /* USBH_PEN */
  67                 vin-supply = <&reg_5v0>;
  68         };
  69 };
  70
  71 &adc1 {
  72         num-channels = <10>;
  73         vref-supply = <&reg_module_3v3_avdd>;
  74 };
  75
  76 /* Colibri SPI */
  77 &ecspi1 {
  78         cs-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>;
  79         pinctrl-names = "default";
  80         pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
  81 };
  82
  83 /* Ethernet */
  84 &fec2 {
  85         pinctrl-names = "default";
  86         pinctrl-0 = <&pinctrl_enet2>;
  87         phy-mode = "rmii";
  88         phy-handle = <&ethphy1>;
  89         status = "okay";
  90
  91         mdio {
  92                 #address-cells = <1>;
  93                 #size-cells = <0>;
  94
  95                 ethphy1: ethernet-phy@2 {
  96                         compatible = "ethernet-phy-ieee802.3-c22";
  97                         max-speed = <100>;
  98                         reg = <2>;
  99                 };
 100         };
 101 };
 102
 103 /* NAND */
 104 &gpmi {
 105         pinctrl-names = "default";
 106         pinctrl-0 = <&pinctrl_gpmi_nand>;
 107         nand-on-flash-bbt;
 108         nand-ecc-mode = "hw";
 109         nand-ecc-strength = <8>;
 110         nand-ecc-step-size = <512>;
 111         status = "okay";
 112 };
 113
 114 /*
 115  * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
 116  */
 117 &i2c1 {
 118         pinctrl-names = "default", "gpio";
 119         pinctrl-0 = <&pinctrl_i2c1>;
 120         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 121         sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 122         scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 123         status = "okay";
 124 };
 125
 126 /*
 127  * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
 128  * touch screen controller
 129  */
 130 &i2c2 {
 131         pinctrl-names = "default", "gpio";
 132         pinctrl-0 = <&pinctrl_i2c2>;
 133         pinctrl-1 = <&pinctrl_i2c2_gpio>;
 134         sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 135         scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 136         status = "okay";
 137
 138         ad7879@2c {
 139                 compatible = "adi,ad7879-1";
 140                 pinctrl-names = "default";
 141                 pinctrl-0 = <&pinctrl_snvs_ad7879_int>;
 142                 reg = <0x2c>;
 143                 interrupt-parent = <&gpio5>;
 144                 interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
 145                 touchscreen-max-pressure = <4096>;
 146                 adi,resistance-plate-x = <120>;
 147                 adi,first-conversion-delay = /bits/ 8 <3>;
 148                 adi,acquisition-time = /bits/ 8 <1>;
 149                 adi,median-filter-size = /bits/ 8 <2>;
 150                 adi,averaging = /bits/ 8 <1>;
 151                 adi,conversion-interval = /bits/ 8 <255>;
 152         };
 153 };
 154
 155 &lcdif {
 156         pinctrl-names = "default";
 157         pinctrl-0 = <&pinctrl_lcdif_dat
 158                      &pinctrl_lcdif_ctrl>;
 159 };
 160
 161 /* PWM <A> */
 162 &pwm4 {
 163         pinctrl-names = "default";
 164         pinctrl-0 = <&pinctrl_pwm4>;
 165         #pwm-cells = <3>;
 166 };
 167
 168 /* PWM <B> */
 169 &pwm5 {
 170         pinctrl-names = "default";
 171         pinctrl-0 = <&pinctrl_pwm5>;
 172         #pwm-cells = <3>;
 173 };
 174
 175 /* PWM <C> */
 176 &pwm6 {
 177         pinctrl-names = "default";
 178         pinctrl-0 = <&pinctrl_pwm6>;
 179         #pwm-cells = <3>;
 180 };
 181
 182 /* PWM <D> */
 183 &pwm7 {
 184         pinctrl-names = "default";
 185         pinctrl-0 = <&pinctrl_pwm7>;
 186         #pwm-cells = <3>;
 187 };
 188
 189 &sdma {
 190         status = "okay";
 191 };
 192
 193 &snvs_pwrkey {
 194         status = "disabled";
 195 };
 196
 197 /* Colibri UART_A */
 198 &uart1 {
 199         pinctrl-names = "default";
 200         pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
 201         uart-has-rtscts;
 202         fsl,dte-mode;
 203         status = "okay";
 204 };
 205
 206 /* Colibri UART_B */
 207 &uart2 {
 208         pinctrl-names = "default";
 209         pinctrl-0 = <&pinctrl_uart2>;
 210         uart-has-rtscts;
 211         fsl,dte-mode;
 212 };
 213
 214 /* Colibri UART_C */
 215 &uart5 {
 216         pinctrl-names = "default";
 217         pinctrl-0 = <&pinctrl_uart5>;
 218         fsl,dte-mode;
 219 };
 220
 221 /* Colibri USBC */
 222 &usbotg1 {
 223         dr_mode = "otg";
 224         srp-disable;
 225         hnp-disable;
 226         adp-disable;
 227         status = "okay";
 228 };
 229
 230 /* Colibri USBH */
 231 &usbotg2 {
 232         dr_mode = "host";
 233         vbus-supply = <&reg_usbh_vbus>;
 234         status = "okay";
 235 };
 236
 237 /* Colibri MMC */
 238 &usdhc1 {
 239         assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
 240         assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
 241         assigned-clock-rates = <0>, <198000000>;
 242         cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */
 243         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 244         pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
 245         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 246         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 247         vmmc-supply = <&reg_sd1_vmmc>;
 248         status = "okay";
 249 };
 250
 251 &iomuxc {
 252         pinctrl_can_int: canint-grp {
 253                 fsl,pins = <
 254                         /* SODIMM 73 */
 255                         MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04    0X14
 256                 >;
 257         };
 258
 259         pinctrl_enet2: enet2-grp {
 260                 fsl,pins = <
 261                         MX6UL_PAD_GPIO1_IO06__ENET2_MDIO        0x1b0b0
 262                         MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0x1b0b0
 263                         MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
 264                         MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
 265                         MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
 266                         MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
 267                         MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
 268                         MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
 269                         MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
 270                         MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
 271                 >;
 272         };
 273
 274         pinctrl_ecspi1_cs: ecspi1-cs-grp {
 275                 fsl,pins = <
 276                         MX6UL_PAD_LCD_DATA21__GPIO3_IO26        0x000a0
 277                 >;
 278         };
 279
 280         pinctrl_ecspi1: ecspi1-grp {
 281                 fsl,pins = <
 282                         MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK       0x000a0
 283                         MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI       0x000a0
 284                         MX6UL_PAD_LCD_DATA23__ECSPI1_MISO       0x100a0
 285                 >;
 286         };
 287
 288         pinctrl_flexcan2: flexcan2-grp {
 289                 fsl,pins = <
 290                         MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX   0x1b020
 291                         MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX      0x1b020
 292                 >;
 293         };
 294
 295         pinctrl_gpio_bl_on: gpio-bl-on-grp {
 296                 fsl,pins = <
 297                         MX6UL_PAD_JTAG_TMS__GPIO1_IO11          0x000a0
 298                 >;
 299         };
 300
 301         pinctrl_gpio1: gpio1-grp {
 302                 fsl,pins = <
 303                         MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00    0x74 /* SODIMM 55 */
 304                         MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01    0x74 /* SODIMM 63 */
 305                         MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25     0X14 /* SODIMM 77 */
 306                         MX6UL_PAD_JTAG_TCK__GPIO1_IO14          0x14 /* SODIMM 99 */
 307                         MX6UL_PAD_NAND_CE1_B__GPIO4_IO14        0x14 /* SODIMM 133 */
 308                         MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24     0x14 /* SODIMM 135 */
 309                         MX6UL_PAD_UART3_CTS_B__GPIO1_IO26       0x14 /* SODIMM 100 */
 310                         MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15       0x14 /* SODIMM 102 */
 311                         MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07       0x14 /* SODIMM 104 */
 312                         MX6UL_PAD_UART3_RTS_B__GPIO1_IO27       0x14 /* SODIMM 186 */
 313                 >;
 314         };
 315
 316         pinctrl_gpio2: gpio2-grp { /* Camera */
 317                 fsl,pins = <
 318                         MX6UL_PAD_CSI_DATA04__GPIO4_IO25        0x74 /* SODIMM 69 */
 319                         MX6UL_PAD_CSI_MCLK__GPIO4_IO17          0x14 /* SODIMM 75 */
 320                         MX6UL_PAD_CSI_DATA06__GPIO4_IO27        0x14 /* SODIMM 85 */
 321                         MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18        0x14 /* SODIMM 96 */
 322                         MX6UL_PAD_CSI_DATA05__GPIO4_IO26        0x14 /* SODIMM 98 */
 323                 >;
 324         };
 325
 326         pinctrl_gpio3: gpio3-grp { /* CAN2 */
 327                 fsl,pins = <
 328                         MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02       0x14 /* SODIMM 178 */
 329                         MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03    0x14 /* SODIMM 188 */
 330                 >;
 331         };
 332
 333         pinctrl_gpio4: gpio4-grp {
 334                 fsl,pins = <
 335                         MX6UL_PAD_CSI_DATA07__GPIO4_IO28        0x74 /* SODIMM 65 */
 336                 >;
 337         };
 338
 339         pinctrl_gpio5: gpio5-grp { /* ATMEL MXT TOUCH */
 340                 fsl,pins = <
 341                         MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0x74 /* SODIMM 106 */
 342                 >;
 343         };
 344
 345         pinctrl_gpio6: gpio6-grp { /* Wifi pins */
 346                 fsl,pins = <
 347                         MX6UL_PAD_GPIO1_IO03__GPIO1_IO03        0x14 /* SODIMM 89 */
 348                         MX6UL_PAD_CSI_DATA02__GPIO4_IO23        0x14 /* SODIMM 79 */
 349                         MX6UL_PAD_CSI_VSYNC__GPIO4_IO19         0x14 /* SODIMM 81 */
 350                         MX6UL_PAD_CSI_DATA03__GPIO4_IO24        0x14 /* SODIMM 97 */
 351                         MX6UL_PAD_CSI_DATA00__GPIO4_IO21        0x14 /* SODIMM 101 */
 352                         MX6UL_PAD_CSI_DATA01__GPIO4_IO22        0x14 /* SODIMM 103 */
 353                         MX6UL_PAD_CSI_HSYNC__GPIO4_IO20         0x14 /* SODIMM 94 */
 354                 >;
 355         };
 356
 357         pinctrl_gpmi_nand: gpmi-nand-grp {
 358                 fsl,pins = <
 359                         MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0x100a9
 360                         MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0x100a9
 361                         MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0x100a9
 362                         MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0x100a9
 363                         MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0x100a9
 364                         MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0x100a9
 365                         MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0x100a9
 366                         MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0x100a9
 367                         MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0x100a9
 368                         MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0x100a9
 369                         MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0x100a9
 370                         MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0x100a9
 371                         MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0x100a9
 372                         MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9
 373                 >;
 374         };
 375
 376         pinctrl_i2c1: i2c1-grp {
 377                 fsl,pins = <
 378                         MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
 379                         MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
 380                 >;
 381         };
 382
 383         pinctrl_i2c1_gpio: i2c1-gpio-grp {
 384                 fsl,pins = <
 385                         MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0
 386                         MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0
 387                 >;
 388         };
 389
 390         pinctrl_i2c2: i2c2-grp {
 391                 fsl,pins = <
 392                         MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
 393                         MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
 394                 >;
 395         };
 396
 397         pinctrl_i2c2_gpio: i2c2-gpio-grp {
 398                 fsl,pins = <
 399                         MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0
 400                         MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0
 401                 >;
 402         };
 403
 404         pinctrl_lcdif_dat: lcdif-dat-grp {
 405                 fsl,pins = <
 406                         MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x00079
 407                         MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x00079
 408                         MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x00079
 409                         MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x00079
 410                         MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x00079
 411                         MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x00079
 412                         MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x00079
 413                         MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x00079
 414                         MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x00079
 415                         MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x00079
 416                         MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x00079
 417                         MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x00079
 418                         MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x00079
 419                         MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x00079
 420                         MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x00079
 421                         MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x00079
 422                         MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x00079
 423                         MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x00079
 424                 >;
 425         };
 426
 427         pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
 428                 fsl,pins = <
 429                         MX6UL_PAD_LCD_CLK__LCDIF_CLK        0x00079
 430                         MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x00079
 431                         MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x00079
 432                         MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x00079
 433                 >;
 434         };
 435
 436         pinctrl_pwm4: pwm4-grp {
 437                 fsl,pins = <
 438                         MX6UL_PAD_NAND_WP_B__PWM4_OUT   0x00079
 439                 >;
 440         };
 441
 442         pinctrl_pwm5: pwm5-grp {
 443                 fsl,pins = <
 444                         MX6UL_PAD_NAND_DQS__PWM5_OUT    0x00079
 445                 >;
 446         };
 447
 448         pinctrl_pwm6: pwm6-grp {
 449                 fsl,pins = <
 450                         MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079
 451                 >;
 452         };
 453
 454         pinctrl_pwm7: pwm7-grp {
 455                 fsl,pins = <
 456                         MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT        0x00079
 457                 >;
 458         };
 459
 460         pinctrl_uart1: uart1-grp {
 461                 fsl,pins = <
 462                         MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX   0x1b0b1
 463                         MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX   0x1b0b1
 464                         MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS    0x1b0b1
 465                         MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS    0x1b0b1
 466                 >;
 467         };
 468
 469         pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */
 470                 fsl,pins = <
 471                         MX6UL_PAD_JTAG_TDI__GPIO1_IO13          0x1b0b1 /* DCD */
 472                         MX6UL_PAD_LCD_DATA18__GPIO3_IO23        0x1b0b1 /* DSR */
 473                         MX6UL_PAD_JTAG_TDO__GPIO1_IO12          0x1b0b1 /* DTR */
 474                         MX6UL_PAD_LCD_DATA19__GPIO3_IO24        0x1b0b1 /* RI */
 475                 >;
 476         };
 477
 478         pinctrl_uart2: uart2-grp {
 479                 fsl,pins = <
 480                         MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX   0x1b0b1
 481                         MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX   0x1b0b1
 482                         MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS    0x1b0b1
 483                         MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS    0x1b0b1
 484                 >;
 485         };
 486         pinctrl_uart5: uart5-grp {
 487                 fsl,pins = <
 488                         MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX      0x1b0b1
 489                         MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX      0x1b0b1
 490                 >;
 491         };
 492
 493         pinctrl_usbh_reg: gpio-usbh-reg {
 494                 fsl,pins = <
 495                         MX6UL_PAD_GPIO1_IO02__GPIO1_IO02        0x1b0b1 /* SODIMM 129 USBH PEN */
 496                 >;
 497         };
 498
 499         pinctrl_usdhc1: usdhc1-grp {
 500                 fsl,pins = <
 501                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x17059
 502                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x10059
 503                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x17059
 504                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x17059
 505                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x17059
 506                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x17059
 507                 >;
 508         };
 509
 510         pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
 511                 fsl,pins = <
 512                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x170b9
 513                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x100b9
 514                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x170b9
 515                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x170b9
 516                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x170b9
 517                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x170b9
 518                 >;
 519         };
 520
 521         pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
 522                 fsl,pins = <
 523                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x170f9
 524                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x100f9
 525                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x170b9
 526                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x170b9
 527                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x170b9
 528                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x170b9
 529                 >;
 530         };
 531
 532         pinctrl_usdhc2: usdhc2-grp {
 533                 fsl,pins = <
 534                         MX6UL_PAD_CSI_DATA00__USDHC2_DATA0      0x17059
 535                         MX6UL_PAD_CSI_DATA01__USDHC2_DATA1      0x17059
 536                         MX6UL_PAD_CSI_DATA02__USDHC2_DATA2      0x17059
 537                         MX6UL_PAD_CSI_DATA03__USDHC2_DATA3      0x17059
 538                         MX6UL_PAD_CSI_HSYNC__USDHC2_CMD         0x17059
 539                         MX6UL_PAD_CSI_VSYNC__USDHC2_CLK         0x17059
 540
 541                         MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT    0x14
 542                 >;
 543         };
 544 };
 545
 546 &iomuxc_snvs {
 547         pinctrl_snvs_gpio1: snvs-gpio1-grp {
 548                 fsl,pins = <
 549                         MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06     0x14 /* SODIMM 93 */
 550                         MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03     0x14 /* SODIMM 95 */
 551                         MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10       0x74 /* SODIMM 105 */
 552                         MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05     0x14 /* SODIMM 131 USBH OC */
 553                         MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08     0x74 /* SODIMM 138 */
 554                 >;
 555         };
 556
 557         pinctrl_snvs_gpio2: snvs-gpio2-grp { /* ATMEL MXT TOUCH */
 558                 fsl,pins = <
 559                         MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04     0x74 /* SODIMM 107 */
 560                 >;
 561         };
 562
 563         pinctrl_snvs_gpio3: snvs-gpio3-grp { /* Wifi pins */
 564                 fsl,pins = <
 565                         MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11       0x14 /* SODIMM 127 */
 566                 >;
 567         };
 568
 569         pinctrl_snvs_ad7879_int: snvs-ad7879-int-grp { /* TOUCH Interrupt */
 570                 fsl,pins = <
 571                         MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07     0x1b0b0
 572                 >;
 573         };
 574
 575         pinctrl_snvs_reg_sd: snvs-reg-sd-grp {
 576                 fsl,pins = <
 577                         MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09     0x4001b8b0
 578                 >;
 579         };
 580
 581         pinctrl_snvs_usbc_det: snvs-usbc-det-grp {
 582                 fsl,pins = <
 583                         MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02     0x1b0b0
 584                 >;
 585         };
 586
 587         pinctrl_snvs_gpiokeys: snvs-gpiokeys-grp {
 588                 fsl,pins = <
 589                         MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01     0x130b0
 590                 >;
 591         };
 592
 593         pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp {
 594                 fsl,pins = <
 595                         MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00     0x1b0b0 /* CD */
 596                 >;
 597         };
 598
 599         pinctrl_snvs_wifi_pdn: snvs-wifi-pdn-grp {
 600                 fsl,pins = <
 601                         MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11       0x14
 602                 >;
 603         };
 604 };