arch/arm/dts/imx6ull-14x14-evk.dts

   1 /*
   2  * Copyright (C) 2016 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /dts-v1/;
  10
  11 #include "imx6ull.dtsi"
  12
  13 / {
  14         model = "Freescale i.MX6 ULL 14x14 EVK Board";
  15         compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
  16
  17         chosen {
  18                 stdout-path = &uart1;
  19         };
  20
  21         memory {
  22                 reg = <0x80000000 0x20000000>;
  23         };
  24
  25         backlight {
  26                 compatible = "pwm-backlight";
  27                 pwms = <&pwm1 0 5000000>;
  28                 brightness-levels = <0 4 8 16 32 64 128 255>;
  29                 default-brightness-level = <6>;
  30                 status = "okay";
  31         };
  32
  33         regulators {
  34                 compatible = "simple-bus";
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 reg_can_3v3: regulator@0 {
  39                         compatible = "regulator-fixed";
  40                         reg = <0>;
  41                         regulator-name = "can-3v3";
  42                         regulator-min-microvolt = <3300000>;
  43                         regulator-max-microvolt = <3300000>;
  44                         gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
  45                 };
  46
  47                 reg_sd1_vmmc: regulator@1 {
  48                         compatible = "regulator-fixed";
  49                         regulator-name = "VSD_3V3";
  50                         regulator-min-microvolt = <3300000>;
  51                         regulator-max-microvolt = <3300000>;
  52                         gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  53                         enable-active-high;
  54                 };
  55
  56                 reg_gpio_dvfs: regulator-gpio {
  57                         compatible = "regulator-gpio";
  58                         pinctrl-names = "default";
  59                         pinctrl-0 = <&pinctrl_dvfs>;
  60                         regulator-min-microvolt = <1300000>;
  61                         regulator-max-microvolt = <1400000>;
  62                         regulator-name = "gpio_dvfs";
  63                         regulator-type = "voltage";
  64                         gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
  65                         states = <1300000 0x1 1400000 0x0>;
  66                 };
  67         };
  68
  69         spi5 {
  70                 compatible = "spi-gpio";
  71                 pinctrl-names = "default";
  72                 pinctrl-0 = <&pinctrl_spi4>;
  73                 status = "okay";
  74                 gpio-sck = <&gpio5 11 0>;
  75                 gpio-mosi = <&gpio5 10 0>;
  76                 cs-gpios = <&gpio5 7 0>;
  77                 num-chipselects = <1>;
  78                 #address-cells = <1>;
  79                 #size-cells = <0>;
  80
  81                 gpio_spi: gpio_spi@0 {
  82                         compatible = "fairchild,74hc595";
  83                         gpio-controller;
  84                         oe-gpios = <&gpio5 8 0>;
  85                         #gpio-cells = <2>;
  86                         reg = <0>;
  87                         registers-number = <1>;
  88                         registers-default = /bits/ 8 <0x57>;
  89                         spi-max-frequency = <100000>;
  90                 };
  91         };
  92 };
  93
  94 &cpu0 {
  95         arm-supply = <&reg_arm>;
  96         soc-supply = <&reg_soc>;
  97         dc-supply = <&reg_gpio_dvfs>;
  98 };
  99
 100 &clks {
 101         assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
 102         assigned-clock-rates = <786432000>;
 103 };
 104
 105 &fec1 {
 106         pinctrl-names = "default";
 107         pinctrl-0 = <&pinctrl_enet1>;
 108         phy-mode = "rmii";
 109         phy-handle = <&ethphy0>;
 110         status = "okay";
 111 };
 112
 113 &fec2 {
 114         pinctrl-names = "default";
 115         pinctrl-0 = <&pinctrl_enet2>;
 116         phy-mode = "rmii";
 117         phy-handle = <&ethphy1>;
 118         status = "okay";
 119
 120         mdio {
 121                 #address-cells = <1>;
 122                 #size-cells = <0>;
 123
 124                 ethphy0: ethernet-phy@2 {
 125                         compatible = "ethernet-phy-ieee802.3-c22";
 126                         reg = <2>;
 127                 };
 128
 129                 ethphy1: ethernet-phy@1 {
 130                         compatible = "ethernet-phy-ieee802.3-c22";
 131                         reg = <1>;
 132                 };
 133         };
 134 };
 135
 136 &gpc {
 137         fsl,cpu_pupscr_sw2iso = <0x1>;
 138         fsl,cpu_pupscr_sw = <0x0>;
 139         fsl,cpu_pdnscr_iso2sw = <0x1>;
 140         fsl,cpu_pdnscr_iso = <0x1>;
 141         fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */
 142 };
 143
 144 &i2c1 {
 145         clock-frequency = <100000>;
 146         pinctrl-names = "default";
 147         pinctrl-0 = <&pinctrl_i2c1>;
 148         status = "okay";
 149
 150         mag3110@0e {
 151                 compatible = "fsl,mag3110";
 152                 reg = <0x0e>;
 153                 position = <2>;
 154         };
 155
 156         fxls8471@1e {
 157                 compatible = "fsl,fxls8471";
 158                 reg = <0x1e>;
 159                 position = <0>;
 160                 interrupt-parent = <&gpio5>;
 161                 interrupts = <0 8>;
 162         };
 163 };
 164
 165 &i2c2 {
 166         clock_frequency = <100000>;
 167         pinctrl-names = "default";
 168         pinctrl-0 = <&pinctrl_i2c2>;
 169         status = "okay";
 170 };
 171
 172 &iomuxc {
 173         pinctrl-names = "default";
 174         pinctrl-0 = <&pinctrl_hog_1>;
 175         imx6ul-evk {
 176                 pinctrl_hog_1: hoggrp-1 {
 177                         fsl,pins = <
 178                                 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059 /* SD1 CD */
 179                                 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT    0x17059 /* SD1 VSELECT */
 180                                 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
 181                         >;
 182                 };
 183
 184                 pinctrl_csi1: csi1grp {
 185                         fsl,pins = <
 186                                 MX6UL_PAD_CSI_MCLK__CSI_MCLK            0x1b088
 187                                 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK        0x1b088
 188                                 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC          0x1b088
 189                                 MX6UL_PAD_CSI_HSYNC__CSI_HSYNC          0x1b088
 190                                 MX6UL_PAD_CSI_DATA00__CSI_DATA02        0x1b088
 191                                 MX6UL_PAD_CSI_DATA01__CSI_DATA03        0x1b088
 192                                 MX6UL_PAD_CSI_DATA02__CSI_DATA04        0x1b088
 193                                 MX6UL_PAD_CSI_DATA03__CSI_DATA05        0x1b088
 194                                 MX6UL_PAD_CSI_DATA04__CSI_DATA06        0x1b088
 195                                 MX6UL_PAD_CSI_DATA05__CSI_DATA07        0x1b088
 196                                 MX6UL_PAD_CSI_DATA06__CSI_DATA08        0x1b088
 197                                 MX6UL_PAD_CSI_DATA07__CSI_DATA09        0x1b088
 198                         >;
 199                 };
 200
 201                 pinctrl_enet1: enet1grp {
 202                         fsl,pins = <
 203                                 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
 204                                 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
 205                                 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
 206                                 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
 207                                 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
 208                                 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
 209                                 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
 210                                 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
 211                         >;
 212                 };
 213
 214                 pinctrl_enet2: enet2grp {
 215                         fsl,pins = <
 216                                 MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0x1b0b0
 217                                 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO        0x1b0b0
 218                                 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
 219                                 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
 220                                 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
 221                                 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
 222                                 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
 223                                 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
 224                                 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
 225                                 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
 226                         >;
 227                 };
 228
 229                 pinctrl_flexcan1: flexcan1grp{
 230                         fsl,pins = <
 231                                 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x1b020
 232                                 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x1b020
 233                         >;
 234                 };
 235
 236                 pinctrl_flexcan2: flexcan2grp{
 237                         fsl,pins = <
 238                                 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX      0x1b020
 239                                 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX      0x1b020
 240                         >;
 241                 };
 242
 243                 pinctrl_i2c1: i2c1grp {
 244                         fsl,pins = <
 245                                 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
 246                                 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
 247                         >;
 248                 };
 249
 250                 pinctrl_i2c2: i2c2grp {
 251                         fsl,pins = <
 252                                 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
 253                                 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
 254                         >;
 255                 };
 256
 257                 pinctrl_lcdif_dat: lcdifdatgrp {
 258                         fsl,pins = <
 259                                 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
 260                                 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
 261                                 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
 262                                 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
 263                                 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
 264                                 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
 265                                 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
 266                                 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
 267                                 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
 268                                 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
 269                                 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
 270                                 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
 271                                 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
 272                                 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
 273                                 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
 274                                 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
 275                                 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
 276                                 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
 277                                 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18  0x79
 278                                 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19  0x79
 279                                 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20  0x79
 280                                 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21  0x79
 281                                 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22  0x79
 282                                 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23  0x79
 283                         >;
 284                 };
 285
 286                 pinctrl_lcdif_ctrl: lcdifctrlgrp {
 287                         fsl,pins = <
 288                                 MX6UL_PAD_LCD_CLK__LCDIF_CLK        0x79
 289                                 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
 290                                 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
 291                                 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
 292                         >;
 293                 };
 294
 295                 pinctrl_pwm1: pwm1grp {
 296                         fsl,pins = <
 297                                 MX6UL_PAD_GPIO1_IO08__PWM1_OUT   0x110b0
 298                         >;
 299                 };
 300
 301                 pinctrl_qspi: qspigrp {
 302                         fsl,pins = <
 303                                 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK      0x70a1
 304                                 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
 305                                 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01   0x70a1
 306                                 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02   0x70a1
 307                                 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03     0x70a1
 308                                 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B      0x70a1
 309                         >;
 310                 };
 311
 312                 pinctrl_uart1: uart1grp {
 313                         fsl,pins = <
 314                                 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
 315                                 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
 316                         >;
 317                 };
 318
 319                 pinctrl_uart2: uart2grp {
 320                         fsl,pins = <
 321                                 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x1b0b1
 322                                 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x1b0b1
 323                                 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS  0x1b0b1
 324                                 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS  0x1b0b1
 325                         >;
 326                 };
 327
 328                 pinctrl_uart2dte: uart2dtegrp {
 329                         fsl,pins = <
 330                                 MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX   0x1b0b1
 331                                 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX   0x1b0b1
 332                                 MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS  0x1b0b1
 333                                 MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS  0x1b0b1
 334                         >;
 335                 };
 336
 337                 pinctrl_usdhc1: usdhc1grp {
 338                         fsl,pins = <
 339                                 MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059
 340                                 MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x10071
 341                                 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
 342                                 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
 343                                 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
 344                                 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
 345                         >;
 346                 };
 347
 348                 pinctrl_usdhc2: usdhc2grp {
 349                         fsl,pins = <
 350                                 MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x10069
 351                                 MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
 352                                 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
 353                                 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
 354                                 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
 355                                 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
 356                         >;
 357                 };
 358
 359                 pinctrl_wdog: wdoggrp {
 360                         fsl,pins = <
 361                                 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
 362                         >;
 363                 };
 364         };
 365 };
 366
 367 &iomuxc_snvs {
 368         pinctrl-names = "default_snvs";
 369         pinctrl-0 = <&pinctrl_hog_2>;
 370         imx6ul-evk {
 371                 pinctrl_hog_2: hoggrp-2 {
 372                         fsl,pins = <
 373                                 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x80000000
 374                         >;
 375                 };
 376
 377                 pinctrl_dvfs: dvfsgrp {
 378                         fsl,pins = <
 379                                 MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03      0x79
 380                         >;
 381                 };
 382
 383                 pinctrl_lcdif_reset: lcdifresetgrp {
 384                         fsl,pins = <
 385                                 /* used for lcd reset */
 386                                 MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09  0x79
 387                         >;
 388                 };
 389
 390                 pinctrl_spi4: spi4grp {
 391                         fsl,pins = <
 392                                 MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10        0x70a1
 393                                 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11        0x70a1
 394                                 MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07      0x70a1
 395                                 MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08      0x80000000
 396                         >;
 397                 };
 398
 399                 pinctrl_sai2_hp_det_b: sai2_hp_det_grp {
 400                         fsl,pins = <
 401                                 MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04   0x17059
 402                         >;
 403                 };
 404         };
 405 };
 406
 407
 408 &lcdif {
 409         pinctrl-names = "default";
 410         pinctrl-0 = <&pinctrl_lcdif_dat
 411                      &pinctrl_lcdif_ctrl
 412                      &pinctrl_lcdif_reset>;
 413         display = <&display0>;
 414         status = "okay";
 415
 416         display0: display {
 417                 bits-per-pixel = <16>;
 418                 bus-width = <24>;
 419
 420                 display-timings {
 421                         native-mode = <&timing0>;
 422                         timing0: timing0 {
 423                         clock-frequency = <9200000>;
 424                         hactive = <480>;
 425                         vactive = <272>;
 426                         hfront-porch = <8>;
 427                         hback-porch = <4>;
 428                         hsync-len = <41>;
 429                         vback-porch = <2>;
 430                         vfront-porch = <4>;
 431                         vsync-len = <10>;
 432
 433                         hsync-active = <0>;
 434                         vsync-active = <0>;
 435                         de-active = <1>;
 436                         pixelclk-active = <0>;
 437                         };
 438                 };
 439         };
 440 };
 441
 442 &pwm1 {
 443         pinctrl-names = "default";
 444         pinctrl-0 = <&pinctrl_pwm1>;
 445         status = "okay";
 446 };
 447
 448 &qspi {
 449         pinctrl-names = "default";
 450         pinctrl-0 = <&pinctrl_qspi>;
 451         status = "okay";
 452         ddrsmp=<0>;
 453
 454         flash0: n25q256a@0 {
 455                 #address-cells = <1>;
 456                 #size-cells = <1>;
 457                 /* compatible = "micron,n25q256a"; */
 458                 compatible = "jedec,spi-nor";
 459                 spi-max-frequency = <29000000>;
 460                 spi-nor,ddr-quad-read-dummy = <6>;
 461                 reg = <0>;
 462         };
 463 };
 464
 465 &uart1 {
 466         pinctrl-names = "default";
 467         pinctrl-0 = <&pinctrl_uart1>;
 468         status = "okay";
 469 };
 470
 471 &uart2 {
 472         pinctrl-names = "default";
 473         pinctrl-0 = <&pinctrl_uart2>;
 474         fsl,uart-has-rtscts;
 475         /* for DTE mode, add below change */
 476         /* fsl,dte-mode; */
 477         /* pinctrl-0 = <&pinctrl_uart2dte>; */
 478         status = "okay";
 479 };
 480
 481 &usbotg1 {
 482         dr_mode = "otg";
 483         srp-disable;
 484         hnp-disable;
 485         adp-disable;
 486         status = "okay";
 487 };
 488
 489 &usbotg2 {
 490         dr_mode = "host";
 491         disable-over-current;
 492         status = "okay";
 493 };
 494
 495 &usbphy1 {
 496         tx-d-cal = <0x5>;
 497 };
 498
 499 &usbphy2 {
 500         tx-d-cal = <0x5>;
 501 };
 502
 503 &usdhc1 {
 504         pinctrl-names = "default";
 505         pinctrl-0 = <&pinctrl_usdhc1>;
 506         cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
 507         keep-power-in-suspend;
 508         enable-sdio-wakeup;
 509         vmmc-supply = <&reg_sd1_vmmc>;
 510         status = "okay";
 511 };
 512
 513 &usdhc2 {
 514         pinctrl-names = "default";
 515         pinctrl-0 = <&pinctrl_usdhc2>;
 516         no-1-8-v;
 517         non-removable;
 518         keep-power-in-suspend;
 519         enable-sdio-wakeup;
 520         status = "okay";
 521 };
 522
 523 &wdog1 {
 524         pinctrl-names = "default";
 525         pinctrl-0 = <&pinctrl_wdog>;
 526         fsl,wdog_b;
 527 };