arch/arm/dts/imx6ul-phycore-segin.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018 Collabora Ltd.
   4  *
   5  * Based on dts[i] from Phytec barebox port:
   6  * Copyright (C) 2016 PHYTEC Messtechnik GmbH
   7  * Author: Christian Hemp <c.hemp@phytec.de>
   8  *
   9  * The code contained herein is licensed under the GNU General Public
  10  * License. You may obtain a copy of the GNU General Public License
  11  * Version 2 or later at the following locations:
  12  *
  13  * http://www.opensource.org/licenses/gpl-license.html
  14  * http://www.gnu.org/copyleft/gpl.html
  15  */
  16
  17 /dts-v1/;
  18
  19 #include "imx6ul-pcl063.dtsi"
  20
  21 / {
  22         model = "Phytec phyBOARD-i.MX6UL-Segin SBC";
  23         compatible = "phytec,phyboard-imx6ul-segin", "phytec,imx6ul-pcl063",
  24                      "fsl,imx6ul";
  25 };
  26
  27 &i2c1 {
  28         i2c_rtc: rtc@68 {
  29                 compatible = "microcrystal,rv4162";
  30                 reg = <0x68>;
  31                 status = "okay";
  32         };
  33 };
  34
  35 &uart5 {
  36         pinctrl-names = "default";
  37         pinctrl-0 = <&pinctrl_uart5>;
  38         uart-has-rtscts;
  39         status = "okay";
  40 };
  41
  42 &usbotg1 {
  43         pinctrl-names = "default";
  44         pinctrl-0 = <&pinctrl_usb_otg1_id>;
  45         dr_mode = "otg";
  46         srp-disable;
  47         hnp-disable;
  48         adp-disable;
  49         status = "okay";
  50 };
  51
  52 &usbotg2 {
  53         dr_mode = "host";
  54         disable-over-current;
  55         status = "okay";
  56 };
  57
  58 &iomuxc {
  59         pinctrl-names = "default";
  60
  61         pinctrl_uart5: uart5grp {
  62                 fsl,pins = <
  63                         MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX   0x1b0b1
  64                         MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX   0x1b0b1
  65                         MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS     0x1b0b1
  66                         MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS     0x1b0b1
  67                 >;
  68         };
  69
  70         pinctrl_usb_otg1_id: usbotg1idgrp {
  71                 fsl,pins = <
  72                         MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID    0x17059
  73                 >;
  74         };
  75
  76 };