arch/arm/dts/imx6ul-pcl063.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018 Collabora Ltd.
   4  *
   5  * Based on dts[i] from Phytec barebox port:
   6  * Copyright (C) 2016 PHYTEC Messtechnik GmbH
   7  * Author: Christian Hemp <c.hemp@phytec.de>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "imx6ul.dtsi"
  13
  14 / {
  15         model = "Phytec phyCORE-i.MX6 Ultra Lite SOM";
  16         compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
  17
  18         memory {
  19                 reg = <0x80000000 0x20000000>;
  20         };
  21
  22         chosen {
  23                 stdout-path = &uart1;
  24         };
  25 };
  26
  27 &fec1 {
  28         pinctrl-names = "default";
  29         pinctrl-0 = <&pinctrl_enet1>;
  30         phy-mode = "rmii";
  31         phy-handle = <&ethphy0>;
  32         status = "okay";
  33
  34         mdio: mdio {
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 ethphy0: ethernet-phy@1 {
  39                         reg = <1>;
  40                         micrel,led-mode = <1>;
  41                 };
  42         };
  43 };
  44
  45 &gpmi {
  46         pinctrl-names = "default";
  47         pinctrl-0 = <&pinctrl_gpmi_nand>;
  48         nand-on-flash-bbt;
  49         fsl,no-blockmark-swap;
  50         status = "okay";
  51
  52         #address-cells = <1>;
  53         #size-cells = <1>;
  54
  55         partition@0 {
  56                 label = "uboot";
  57                 reg = <0x0 0x400000>;
  58         };
  59
  60         partition@400000 {
  61                 label = "uboot-env";
  62                 reg = <0x400000 0x100000>;
  63         };
  64
  65         partition@500000 {
  66                 label = "root";
  67                 reg = <0x500000 0x0>;
  68         };
  69 };
  70
  71 &i2c1 {
  72         clock-frequency = <100000>;
  73         pinctrl-names = "default", "gpio";
  74         pinctrl-0 = <&pinctrl_i2c1>;
  75         pinctrl-1 = <&pinctrl_i2c1_gpio>;
  76         scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
  77         sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
  78         status = "okay";
  79
  80         eeprom@52 {
  81                 compatible = "cat,24c32";
  82                 reg = <0x52>;
  83         };
  84 };
  85
  86 &uart1 {
  87         pinctrl-names = "default";
  88         pinctrl-0 = <&pinctrl_uart1>;
  89         status = "okay";
  90 };
  91
  92 &usdhc1 {
  93         pinctrl-names = "default";
  94         pinctrl-0 = <&pinctrl_usdhc1>;
  95         cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
  96         bus-width = <0x4>;
  97         pinctrl-0 = <&pinctrl_usdhc1>;
  98         no-1-8-v;
  99         status = "okay";
 100 };
 101
 102 &iomuxc {
 103         pinctrl-names = "default";
 104
 105         pinctrl_enet1: enet1grp {
 106                 fsl,pins = <
 107                         MX6UL_PAD_GPIO1_IO06__ENET1_MDIO        0x1b0b0
 108                         MX6UL_PAD_GPIO1_IO07__ENET1_MDC         0X1b0b0
 109                         MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
 110                         MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
 111                         MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
 112                         MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
 113                         MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
 114                         MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
 115                         MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
 116                         MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
 117                 >;
 118         };
 119
 120         pinctrl_gpmi_nand: gpminandgrp {
 121                 fsl,pins = <
 122                         MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0x0b0b1
 123                         MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0x0b0b1
 124                         MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0x0b0b1
 125                         MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
 126                         MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0x0b0b1
 127                         MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0x0b0b1
 128                         MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0x0b0b1
 129                         MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0x0b0b1
 130                         MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0x0b0b1
 131                         MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0x0b0b1
 132                         MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0x0b0b1
 133                         MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0x0b0b1
 134                         MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0x0b0b1
 135                         MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0x0b0b1
 136                         MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0x0b0b1
 137                 >;
 138         };
 139
 140         pinctrl_i2c1: i2cgrp {
 141                 fsl,pins = <
 142                         MX6UL_PAD_UART4_TX_DATA__I2C1_SCL       0x4001b8b0
 143                         MX6UL_PAD_UART4_RX_DATA__I2C1_SDA       0x4001b8b0
 144                 >;
 145         };
 146
 147         pinctrl_i2c1_gpio: i2c1grp_gpio {
 148                 fsl,pins = <
 149                         MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0
 150                         MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0
 151                 >;
 152         };
 153
 154         pinctrl_uart1: uart1grp {
 155                 fsl,pins = <
 156                         MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX   0x1b0b1
 157                         MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX   0x1b0b1
 158                 >;
 159         };
 160
 161         pinctrl_usdhc1: usdhc1grp {
 162                 fsl,pins = <
 163                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x17059
 164                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x10059
 165                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x17059
 166                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x17059
 167                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x17059
 168                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x17059
 169                         MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059
 170
 171                 >;
 172         };
 173 };