arm64: zynqmp: Add reset-controller support in serdes driver
[oweals/u-boot.git] / arch / arm / dts / imx6sx.dtsi
1 /*
2  * Copyright 2014 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  */
8
9 #include <dt-bindings/clock/imx6sx-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "imx6sx-pinfunc.h"
14 #include "skeleton.dtsi"
15
16 / {
17         aliases {
18                 can0 = &flexcan1;
19                 can1 = &flexcan2;
20                 ethernet0 = &fec1;
21                 ethernet1 = &fec2;
22                 gpio0 = &gpio1;
23                 gpio1 = &gpio2;
24                 gpio2 = &gpio3;
25                 gpio3 = &gpio4;
26                 gpio4 = &gpio5;
27                 gpio5 = &gpio6;
28                 gpio6 = &gpio7;
29                 i2c0 = &i2c1;
30                 i2c1 = &i2c2;
31                 i2c2 = &i2c3;
32                 i2c3 = &i2c4;
33                 mmc0 = &usdhc1;
34                 mmc1 = &usdhc2;
35                 mmc2 = &usdhc3;
36                 mmc3 = &usdhc4;
37                 serial0 = &uart1;
38                 serial1 = &uart2;
39                 serial2 = &uart3;
40                 serial3 = &uart4;
41                 serial4 = &uart5;
42                 serial5 = &uart6;
43                 spi0 = &ecspi1;
44                 spi1 = &ecspi2;
45                 spi2 = &ecspi3;
46                 spi3 = &ecspi4;
47                 spi4 = &ecspi5;
48                 usbphy0 = &usbphy1;
49                 usbphy1 = &usbphy2;
50         };
51
52         cpus {
53                 #address-cells = <1>;
54                 #size-cells = <0>;
55
56                 cpu0: cpu@0 {
57                         compatible = "arm,cortex-a9";
58                         device_type = "cpu";
59                         reg = <0>;
60                         next-level-cache = <&L2>;
61                         operating-points = <
62                                 /* kHz    uV */
63                                 996000  1250000
64                                 792000  1175000
65                                 396000  1075000
66                                 198000  975000
67                         >;
68                         fsl,soc-operating-points = <
69                                 /* ARM kHz  SOC uV */
70                                 996000      1175000
71                                 792000      1175000
72                                 396000      1175000
73                                 198000      1175000
74                         >;
75                         clock-latency = <61036>; /* two CLK32 periods */
76                         clocks = <&clks IMX6SX_CLK_ARM>,
77                                  <&clks IMX6SX_CLK_PLL2_PFD2>,
78                                  <&clks IMX6SX_CLK_STEP>,
79                                  <&clks IMX6SX_CLK_PLL1_SW>,
80                                  <&clks IMX6SX_CLK_PLL1_SYS>;
81                         clock-names = "arm", "pll2_pfd2_396m", "step",
82                                       "pll1_sw", "pll1_sys";
83                         arm-supply = <&reg_arm>;
84                         soc-supply = <&reg_soc>;
85                 };
86         };
87
88         intc: interrupt-controller@00a01000 {
89                 compatible = "arm,cortex-a9-gic";
90                 #interrupt-cells = <3>;
91                 interrupt-controller;
92                 reg = <0x00a01000 0x1000>,
93                       <0x00a00100 0x100>;
94                 interrupt-parent = <&intc>;
95         };
96
97         clocks {
98                 #address-cells = <1>;
99                 #size-cells = <0>;
100
101                 ckil: clock@0 {
102                         compatible = "fixed-clock";
103                         reg = <0>;
104                         #clock-cells = <0>;
105                         clock-frequency = <32768>;
106                         clock-output-names = "ckil";
107                 };
108
109                 osc: clock@1 {
110                         compatible = "fixed-clock";
111                         reg = <1>;
112                         #clock-cells = <0>;
113                         clock-frequency = <24000000>;
114                         clock-output-names = "osc";
115                 };
116
117                 ipp_di0: clock@2 {
118                         compatible = "fixed-clock";
119                         reg = <2>;
120                         #clock-cells = <0>;
121                         clock-frequency = <0>;
122                         clock-output-names = "ipp_di0";
123                 };
124
125                 ipp_di1: clock@3 {
126                         compatible = "fixed-clock";
127                         reg = <3>;
128                         #clock-cells = <0>;
129                         clock-frequency = <0>;
130                         clock-output-names = "ipp_di1";
131                 };
132         };
133
134         soc {
135                 #address-cells = <1>;
136                 #size-cells = <1>;
137                 compatible = "simple-bus";
138                 interrupt-parent = <&gpc>;
139                 ranges;
140
141                 pmu {
142                         compatible = "arm,cortex-a9-pmu";
143                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
144                 };
145
146                 ocram: sram@00900000 {
147                         compatible = "mmio-sram";
148                         reg = <0x00900000 0x20000>;
149                         clocks = <&clks IMX6SX_CLK_OCRAM>;
150                 };
151
152                 L2: l2-cache@00a02000 {
153                         compatible = "arm,pl310-cache";
154                         reg = <0x00a02000 0x1000>;
155                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
156                         cache-unified;
157                         cache-level = <2>;
158                         arm,tag-latency = <4 2 3>;
159                         arm,data-latency = <4 2 3>;
160                 };
161
162                 gpu: gpu@01800000 {
163                         compatible = "vivante,gc";
164                         reg = <0x01800000 0x4000>;
165                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
166                         clocks = <&clks IMX6SX_CLK_GPU>,
167                                  <&clks IMX6SX_CLK_GPU>,
168                                  <&clks IMX6SX_CLK_GPU>;
169                         clock-names = "bus", "core", "shader";
170                 };
171
172                 dma_apbh: dma-apbh@01804000 {
173                         compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
174                         reg = <0x01804000 0x2000>;
175                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
176                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
177                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
178                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
179                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
180                         #dma-cells = <1>;
181                         dma-channels = <4>;
182                         clocks = <&clks IMX6SX_CLK_APBH_DMA>;
183                 };
184
185                 gpmi: gpmi-nand@01806000{
186                         compatible = "fsl,imx6sx-gpmi-nand";
187                         #address-cells = <1>;
188                         #size-cells = <1>;
189                         reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
190                         reg-names = "gpmi-nand", "bch";
191                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
192                         interrupt-names = "bch";
193                         clocks = <&clks IMX6SX_CLK_GPMI_IO>,
194                                  <&clks IMX6SX_CLK_GPMI_APB>,
195                                  <&clks IMX6SX_CLK_GPMI_BCH>,
196                                  <&clks IMX6SX_CLK_GPMI_BCH_APB>,
197                                  <&clks IMX6SX_CLK_PER1_BCH>;
198                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
199                                       "gpmi_bch_apb", "per1_bch";
200                         dmas = <&dma_apbh 0>;
201                         dma-names = "rx-tx";
202                         status = "disabled";
203                 };
204
205                 aips1: aips-bus@02000000 {
206                         compatible = "fsl,aips-bus", "simple-bus";
207                         #address-cells = <1>;
208                         #size-cells = <1>;
209                         reg = <0x02000000 0x100000>;
210                         ranges;
211
212                         spba-bus@02000000 {
213                                 compatible = "fsl,spba-bus", "simple-bus";
214                                 #address-cells = <1>;
215                                 #size-cells = <1>;
216                                 reg = <0x02000000 0x40000>;
217                                 ranges;
218
219                                 spdif: spdif@02004000 {
220                                         compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
221                                         reg = <0x02004000 0x4000>;
222                                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
223                                         dmas = <&sdma 14 18 0>,
224                                                <&sdma 15 18 0>;
225                                         dma-names = "rx", "tx";
226                                         clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>,
227                                                  <&clks IMX6SX_CLK_OSC>,
228                                                  <&clks IMX6SX_CLK_SPDIF>,
229                                                  <&clks 0>, <&clks 0>, <&clks 0>,
230                                                  <&clks IMX6SX_CLK_IPG>,
231                                                  <&clks 0>, <&clks 0>,
232                                                  <&clks IMX6SX_CLK_SPBA>;
233                                         clock-names = "core", "rxtx0",
234                                                       "rxtx1", "rxtx2",
235                                                       "rxtx3", "rxtx4",
236                                                       "rxtx5", "rxtx6",
237                                                       "rxtx7", "spba";
238                                         status = "disabled";
239                                 };
240
241                                 ecspi1: ecspi@02008000 {
242                                         #address-cells = <1>;
243                                         #size-cells = <0>;
244                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
245                                         reg = <0x02008000 0x4000>;
246                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
247                                         clocks = <&clks IMX6SX_CLK_ECSPI1>,
248                                                  <&clks IMX6SX_CLK_ECSPI1>;
249                                         clock-names = "ipg", "per";
250                                         status = "disabled";
251                                 };
252
253                                 ecspi2: ecspi@0200c000 {
254                                         #address-cells = <1>;
255                                         #size-cells = <0>;
256                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
257                                         reg = <0x0200c000 0x4000>;
258                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
259                                         clocks = <&clks IMX6SX_CLK_ECSPI2>,
260                                                  <&clks IMX6SX_CLK_ECSPI2>;
261                                         clock-names = "ipg", "per";
262                                         status = "disabled";
263                                 };
264
265                                 ecspi3: ecspi@02010000 {
266                                         #address-cells = <1>;
267                                         #size-cells = <0>;
268                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
269                                         reg = <0x02010000 0x4000>;
270                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
271                                         clocks = <&clks IMX6SX_CLK_ECSPI3>,
272                                                  <&clks IMX6SX_CLK_ECSPI3>;
273                                         clock-names = "ipg", "per";
274                                         status = "disabled";
275                                 };
276
277                                 ecspi4: ecspi@02014000 {
278                                         #address-cells = <1>;
279                                         #size-cells = <0>;
280                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
281                                         reg = <0x02014000 0x4000>;
282                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
283                                         clocks = <&clks IMX6SX_CLK_ECSPI4>,
284                                                  <&clks IMX6SX_CLK_ECSPI4>;
285                                         clock-names = "ipg", "per";
286                                         status = "disabled";
287                                 };
288
289                                 uart1: serial@02020000 {
290                                         compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
291                                         reg = <0x02020000 0x4000>;
292                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
293                                         clocks = <&clks IMX6SX_CLK_UART_IPG>,
294                                                  <&clks IMX6SX_CLK_UART_SERIAL>;
295                                         clock-names = "ipg", "per";
296                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
297                                         dma-names = "rx", "tx";
298                                         status = "disabled";
299                                 };
300
301                                 esai: esai@02024000 {
302                                         reg = <0x02024000 0x4000>;
303                                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
304                                         clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
305                                                  <&clks IMX6SX_CLK_ESAI_MEM>,
306                                                  <&clks IMX6SX_CLK_ESAI_EXTAL>,
307                                                  <&clks IMX6SX_CLK_ESAI_IPG>,
308                                                  <&clks IMX6SX_CLK_SPBA>;
309                                         clock-names = "core", "mem", "extal",
310                                                       "fsys", "spba";
311                                         status = "disabled";
312                                 };
313
314                                 ssi1: ssi@02028000 {
315                                         #sound-dai-cells = <0>;
316                                         compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
317                                         reg = <0x02028000 0x4000>;
318                                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
319                                         clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
320                                                  <&clks IMX6SX_CLK_SSI1>;
321                                         clock-names = "ipg", "baud";
322                                         dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
323                                         dma-names = "rx", "tx";
324                                         fsl,fifo-depth = <15>;
325                                         status = "disabled";
326                                 };
327
328                                 ssi2: ssi@0202c000 {
329                                         #sound-dai-cells = <0>;
330                                         compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
331                                         reg = <0x0202c000 0x4000>;
332                                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
333                                         clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
334                                                  <&clks IMX6SX_CLK_SSI2>;
335                                         clock-names = "ipg", "baud";
336                                         dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
337                                         dma-names = "rx", "tx";
338                                         fsl,fifo-depth = <15>;
339                                         status = "disabled";
340                                 };
341
342                                 ssi3: ssi@02030000 {
343                                         #sound-dai-cells = <0>;
344                                         compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
345                                         reg = <0x02030000 0x4000>;
346                                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
347                                         clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
348                                                  <&clks IMX6SX_CLK_SSI3>;
349                                         clock-names = "ipg", "baud";
350                                         dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
351                                         dma-names = "rx", "tx";
352                                         fsl,fifo-depth = <15>;
353                                         status = "disabled";
354                                 };
355
356                                 asrc: asrc@02034000 {
357                                         reg = <0x02034000 0x4000>;
358                                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
359                                         clocks = <&clks IMX6SX_CLK_ASRC_MEM>,
360                                                  <&clks IMX6SX_CLK_ASRC_IPG>,
361                                                  <&clks IMX6SX_CLK_SPDIF>,
362                                                  <&clks IMX6SX_CLK_SPBA>;
363                                         clock-names = "mem", "ipg", "asrck", "spba";
364                                         dmas = <&sdma 17 20 1>, <&sdma 18 20 1>,
365                                                <&sdma 19 20 1>, <&sdma 20 20 1>,
366                                                <&sdma 21 20 1>, <&sdma 22 20 1>;
367                                         dma-names = "rxa", "rxb", "rxc",
368                                                     "txa", "txb", "txc";
369                                         status = "okay";
370                                 };
371                         };
372
373                         pwm1: pwm@02080000 {
374                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
375                                 reg = <0x02080000 0x4000>;
376                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
377                                 clocks = <&clks IMX6SX_CLK_PWM1>,
378                                          <&clks IMX6SX_CLK_PWM1>;
379                                 clock-names = "ipg", "per";
380                                 #pwm-cells = <2>;
381                         };
382
383                         pwm2: pwm@02084000 {
384                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
385                                 reg = <0x02084000 0x4000>;
386                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
387                                 clocks = <&clks IMX6SX_CLK_PWM2>,
388                                          <&clks IMX6SX_CLK_PWM2>;
389                                 clock-names = "ipg", "per";
390                                 #pwm-cells = <2>;
391                         };
392
393                         pwm3: pwm@02088000 {
394                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
395                                 reg = <0x02088000 0x4000>;
396                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
397                                 clocks = <&clks IMX6SX_CLK_PWM3>,
398                                          <&clks IMX6SX_CLK_PWM3>;
399                                 clock-names = "ipg", "per";
400                                 #pwm-cells = <2>;
401                         };
402
403                         pwm4: pwm@0208c000 {
404                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
405                                 reg = <0x0208c000 0x4000>;
406                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
407                                 clocks = <&clks IMX6SX_CLK_PWM4>,
408                                          <&clks IMX6SX_CLK_PWM4>;
409                                 clock-names = "ipg", "per";
410                                 #pwm-cells = <2>;
411                         };
412
413                         flexcan1: can@02090000 {
414                                 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
415                                 reg = <0x02090000 0x4000>;
416                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
417                                 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
418                                          <&clks IMX6SX_CLK_CAN1_SERIAL>;
419                                 clock-names = "ipg", "per";
420                                 status = "disabled";
421                         };
422
423                         flexcan2: can@02094000 {
424                                 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
425                                 reg = <0x02094000 0x4000>;
426                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
427                                 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
428                                          <&clks IMX6SX_CLK_CAN2_SERIAL>;
429                                 clock-names = "ipg", "per";
430                                 status = "disabled";
431                         };
432
433                         gpt: gpt@02098000 {
434                                 compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt";
435                                 reg = <0x02098000 0x4000>;
436                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
437                                 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
438                                          <&clks IMX6SX_CLK_GPT_3M>;
439                                 clock-names = "ipg", "per";
440                         };
441
442                         gpio1: gpio@0209c000 {
443                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
444                                 reg = <0x0209c000 0x4000>;
445                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
446                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
447                                 gpio-controller;
448                                 #gpio-cells = <2>;
449                                 interrupt-controller;
450                                 #interrupt-cells = <2>;
451                                 gpio-ranges = <&iomuxc 0 5 26>;
452                         };
453
454                         gpio2: gpio@020a0000 {
455                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
456                                 reg = <0x020a0000 0x4000>;
457                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
458                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
459                                 gpio-controller;
460                                 #gpio-cells = <2>;
461                                 interrupt-controller;
462                                 #interrupt-cells = <2>;
463                                 gpio-ranges = <&iomuxc 0 31 20>;
464                         };
465
466                         gpio3: gpio@020a4000 {
467                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
468                                 reg = <0x020a4000 0x4000>;
469                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
470                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
471                                 gpio-controller;
472                                 #gpio-cells = <2>;
473                                 interrupt-controller;
474                                 #interrupt-cells = <2>;
475                                 gpio-ranges = <&iomuxc 0 51 29>;
476                         };
477
478                         gpio4: gpio@020a8000 {
479                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
480                                 reg = <0x020a8000 0x4000>;
481                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
482                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
483                                 gpio-controller;
484                                 #gpio-cells = <2>;
485                                 interrupt-controller;
486                                 #interrupt-cells = <2>;
487                                 gpio-ranges = <&iomuxc 0 80 32>;
488                         };
489
490                         gpio5: gpio@020ac000 {
491                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
492                                 reg = <0x020ac000 0x4000>;
493                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
494                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
495                                 gpio-controller;
496                                 #gpio-cells = <2>;
497                                 interrupt-controller;
498                                 #interrupt-cells = <2>;
499                                 gpio-ranges = <&iomuxc 0 112 24>;
500                         };
501
502                         gpio6: gpio@020b0000 {
503                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
504                                 reg = <0x020b0000 0x4000>;
505                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
506                                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
507                                 gpio-controller;
508                                 #gpio-cells = <2>;
509                                 interrupt-controller;
510                                 #interrupt-cells = <2>;
511                                 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
512                         };
513
514                         gpio7: gpio@020b4000 {
515                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
516                                 reg = <0x020b4000 0x4000>;
517                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
518                                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
519                                 gpio-controller;
520                                 #gpio-cells = <2>;
521                                 interrupt-controller;
522                                 #interrupt-cells = <2>;
523                                 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
524                         };
525
526                         kpp: kpp@020b8000 {
527                                 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
528                                 reg = <0x020b8000 0x4000>;
529                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
530                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
531                                 status = "disabled";
532                         };
533
534                         wdog1: wdog@020bc000 {
535                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
536                                 reg = <0x020bc000 0x4000>;
537                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
538                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
539                         };
540
541                         wdog2: wdog@020c0000 {
542                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
543                                 reg = <0x020c0000 0x4000>;
544                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
545                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
546                                 status = "disabled";
547                         };
548
549                         clks: ccm@020c4000 {
550                                 compatible = "fsl,imx6sx-ccm";
551                                 reg = <0x020c4000 0x4000>;
552                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
553                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
554                                 #clock-cells = <1>;
555                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
556                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
557                         };
558
559                         anatop: anatop@020c8000 {
560                                 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
561                                              "syscon", "simple-bus";
562                                 reg = <0x020c8000 0x1000>;
563                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
564                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
565                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
566
567                                 regulator-1p1 {
568                                         compatible = "fsl,anatop-regulator";
569                                         regulator-name = "vdd1p1";
570                                         regulator-min-microvolt = <800000>;
571                                         regulator-max-microvolt = <1375000>;
572                                         regulator-always-on;
573                                         anatop-reg-offset = <0x110>;
574                                         anatop-vol-bit-shift = <8>;
575                                         anatop-vol-bit-width = <5>;
576                                         anatop-min-bit-val = <4>;
577                                         anatop-min-voltage = <800000>;
578                                         anatop-max-voltage = <1375000>;
579                                 };
580
581                                 regulator-3p0 {
582                                         compatible = "fsl,anatop-regulator";
583                                         regulator-name = "vdd3p0";
584                                         regulator-min-microvolt = <2800000>;
585                                         regulator-max-microvolt = <3150000>;
586                                         regulator-always-on;
587                                         anatop-reg-offset = <0x120>;
588                                         anatop-vol-bit-shift = <8>;
589                                         anatop-vol-bit-width = <5>;
590                                         anatop-min-bit-val = <0>;
591                                         anatop-min-voltage = <2625000>;
592                                         anatop-max-voltage = <3400000>;
593                                 };
594
595                                 regulator-2p5 {
596                                         compatible = "fsl,anatop-regulator";
597                                         regulator-name = "vdd2p5";
598                                         regulator-min-microvolt = <2100000>;
599                                         regulator-max-microvolt = <2875000>;
600                                         regulator-always-on;
601                                         anatop-reg-offset = <0x130>;
602                                         anatop-vol-bit-shift = <8>;
603                                         anatop-vol-bit-width = <5>;
604                                         anatop-min-bit-val = <0>;
605                                         anatop-min-voltage = <2100000>;
606                                         anatop-max-voltage = <2875000>;
607                                 };
608
609                                 reg_arm: regulator-vddcore {
610                                         compatible = "fsl,anatop-regulator";
611                                         regulator-name = "vddarm";
612                                         regulator-min-microvolt = <725000>;
613                                         regulator-max-microvolt = <1450000>;
614                                         regulator-always-on;
615                                         anatop-reg-offset = <0x140>;
616                                         anatop-vol-bit-shift = <0>;
617                                         anatop-vol-bit-width = <5>;
618                                         anatop-delay-reg-offset = <0x170>;
619                                         anatop-delay-bit-shift = <24>;
620                                         anatop-delay-bit-width = <2>;
621                                         anatop-min-bit-val = <1>;
622                                         anatop-min-voltage = <725000>;
623                                         anatop-max-voltage = <1450000>;
624                                 };
625
626                                 reg_pcie: regulator-vddpcie {
627                                         compatible = "fsl,anatop-regulator";
628                                         regulator-name = "vddpcie";
629                                         regulator-min-microvolt = <725000>;
630                                         regulator-max-microvolt = <1450000>;
631                                         anatop-reg-offset = <0x140>;
632                                         anatop-vol-bit-shift = <9>;
633                                         anatop-vol-bit-width = <5>;
634                                         anatop-delay-reg-offset = <0x170>;
635                                         anatop-delay-bit-shift = <26>;
636                                         anatop-delay-bit-width = <2>;
637                                         anatop-min-bit-val = <1>;
638                                         anatop-min-voltage = <725000>;
639                                         anatop-max-voltage = <1450000>;
640                                 };
641
642                                 reg_soc: regulator-vddsoc {
643                                         compatible = "fsl,anatop-regulator";
644                                         regulator-name = "vddsoc";
645                                         regulator-min-microvolt = <725000>;
646                                         regulator-max-microvolt = <1450000>;
647                                         regulator-always-on;
648                                         anatop-reg-offset = <0x140>;
649                                         anatop-vol-bit-shift = <18>;
650                                         anatop-vol-bit-width = <5>;
651                                         anatop-delay-reg-offset = <0x170>;
652                                         anatop-delay-bit-shift = <28>;
653                                         anatop-delay-bit-width = <2>;
654                                         anatop-min-bit-val = <1>;
655                                         anatop-min-voltage = <725000>;
656                                         anatop-max-voltage = <1450000>;
657                                 };
658                         };
659
660                         tempmon: tempmon {
661                                 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
662                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
663                                 fsl,tempmon = <&anatop>;
664                                 fsl,tempmon-data = <&ocotp>;
665                                 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
666                         };
667
668                         usbphy1: usbphy@020c9000 {
669                                 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
670                                 reg = <0x020c9000 0x1000>;
671                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
672                                 clocks = <&clks IMX6SX_CLK_USBPHY1>;
673                                 fsl,anatop = <&anatop>;
674                         };
675
676                         usbphy2: usbphy@020ca000 {
677                                 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
678                                 reg = <0x020ca000 0x1000>;
679                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
680                                 clocks = <&clks IMX6SX_CLK_USBPHY2>;
681                                 fsl,anatop = <&anatop>;
682                         };
683
684                         snvs: snvs@020cc000 {
685                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
686                                 reg = <0x020cc000 0x4000>;
687
688                                 snvs_rtc: snvs-rtc-lp {
689                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
690                                         regmap = <&snvs>;
691                                         offset = <0x34>;
692                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
693                                 };
694
695                                 snvs_poweroff: snvs-poweroff {
696                                         compatible = "syscon-poweroff";
697                                         regmap = <&snvs>;
698                                         offset = <0x38>;
699                                         mask = <0x60>;
700                                         status = "disabled";
701                                 };
702
703                                 snvs_pwrkey: snvs-powerkey {
704                                         compatible = "fsl,sec-v4.0-pwrkey";
705                                         regmap = <&snvs>;
706                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
707                                         linux,keycode = <KEY_POWER>;
708                                         wakeup-source;
709                                 };
710                         };
711
712                         epit1: epit@020d0000 {
713                                 reg = <0x020d0000 0x4000>;
714                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
715                         };
716
717                         epit2: epit@020d4000 {
718                                 reg = <0x020d4000 0x4000>;
719                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
720                         };
721
722                         src: src@020d8000 {
723                                 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
724                                 reg = <0x020d8000 0x4000>;
725                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
726                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
727                                 #reset-cells = <1>;
728                         };
729
730                         gpc: gpc@020dc000 {
731                                 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
732                                 reg = <0x020dc000 0x4000>;
733                                 interrupt-controller;
734                                 #interrupt-cells = <3>;
735                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
736                                 interrupt-parent = <&intc>;
737                         };
738
739                         iomuxc: iomuxc@020e0000 {
740                                 compatible = "fsl,imx6sx-iomuxc";
741                                 reg = <0x020e0000 0x4000>;
742                         };
743
744                         gpr: iomuxc-gpr@020e4000 {
745                                 compatible = "fsl,imx6sx-iomuxc-gpr",
746                                              "fsl,imx6q-iomuxc-gpr", "syscon";
747                                 reg = <0x020e4000 0x4000>;
748                         };
749
750                         sdma: sdma@020ec000 {
751                                 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
752                                 reg = <0x020ec000 0x4000>;
753                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
754                                 clocks = <&clks IMX6SX_CLK_SDMA>,
755                                          <&clks IMX6SX_CLK_SDMA>;
756                                 clock-names = "ipg", "ahb";
757                                 #dma-cells = <3>;
758                                 /* imx6sx reuses imx6q sdma firmware */
759                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
760                         };
761                 };
762
763                 aips2: aips-bus@02100000 {
764                         compatible = "fsl,aips-bus", "simple-bus";
765                         #address-cells = <1>;
766                         #size-cells = <1>;
767                         reg = <0x02100000 0x100000>;
768                         ranges;
769
770                         crypto: caam@2100000 {
771                                 compatible = "fsl,sec-v4.0";
772                                 fsl,sec-era = <4>;
773                                 #address-cells = <1>;
774                                 #size-cells = <1>;
775                                 reg = <0x2100000 0x10000>;
776                                 ranges = <0 0x2100000 0x10000>;
777                                 interrupt-parent = <&intc>;
778                                 clocks = <&clks IMX6SX_CLK_CAAM_MEM>,
779                                          <&clks IMX6SX_CLK_CAAM_ACLK>,
780                                          <&clks IMX6SX_CLK_CAAM_IPG>,
781                                          <&clks IMX6SX_CLK_EIM_SLOW>;
782                                 clock-names = "mem", "aclk", "ipg", "emi_slow";
783
784                                 sec_jr0: jr0@1000 {
785                                         compatible = "fsl,sec-v4.0-job-ring";
786                                         reg = <0x1000 0x1000>;
787                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
788                                 };
789
790                                 sec_jr1: jr1@2000 {
791                                         compatible = "fsl,sec-v4.0-job-ring";
792                                         reg = <0x2000 0x1000>;
793                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
794                                 };
795                         };
796
797                         usbotg1: usb@02184000 {
798                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
799                                 reg = <0x02184000 0x200>;
800                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
801                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
802                                 fsl,usbphy = <&usbphy1>;
803                                 fsl,usbmisc = <&usbmisc 0>;
804                                 fsl,anatop = <&anatop>;
805                                 ahb-burst-config = <0x0>;
806                                 tx-burst-size-dword = <0x10>;
807                                 rx-burst-size-dword = <0x10>;
808                                 status = "disabled";
809                         };
810
811                         usbotg2: usb@02184200 {
812                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
813                                 reg = <0x02184200 0x200>;
814                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
815                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
816                                 fsl,usbphy = <&usbphy2>;
817                                 fsl,usbmisc = <&usbmisc 1>;
818                                 ahb-burst-config = <0x0>;
819                                 tx-burst-size-dword = <0x10>;
820                                 rx-burst-size-dword = <0x10>;
821                                 status = "disabled";
822                         };
823
824                         usbh: usb@02184400 {
825                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
826                                 reg = <0x02184400 0x200>;
827                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
828                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
829                                 fsl,usbmisc = <&usbmisc 2>;
830                                 phy_type = "hsic";
831                                 fsl,anatop = <&anatop>;
832                                 dr_mode = "host";
833                                 ahb-burst-config = <0x0>;
834                                 tx-burst-size-dword = <0x10>;
835                                 rx-burst-size-dword = <0x10>;
836                                 status = "disabled";
837                         };
838
839                         usbmisc: usbmisc@02184800 {
840                                 #index-cells = <1>;
841                                 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
842                                 reg = <0x02184800 0x200>;
843                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
844                         };
845
846                         fec1: ethernet@02188000 {
847                                 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
848                                 reg = <0x02188000 0x4000>;
849                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
850                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
851                                 clocks = <&clks IMX6SX_CLK_ENET>,
852                                          <&clks IMX6SX_CLK_ENET_AHB>,
853                                          <&clks IMX6SX_CLK_ENET_PTP>,
854                                          <&clks IMX6SX_CLK_ENET_REF>,
855                                          <&clks IMX6SX_CLK_ENET_PTP>;
856                                 clock-names = "ipg", "ahb", "ptp",
857                                               "enet_clk_ref", "enet_out";
858                                 fsl,num-tx-queues=<3>;
859                                 fsl,num-rx-queues=<3>;
860                                 status = "disabled";
861                         };
862
863                         mlb: mlb@0218c000 {
864                                 reg = <0x0218c000 0x4000>;
865                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
866                                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
867                                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
868                                 clocks = <&clks IMX6SX_CLK_MLB>;
869                                 status = "disabled";
870                         };
871
872                         usdhc1: usdhc@02190000 {
873                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
874                                 reg = <0x02190000 0x4000>;
875                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
876                                 clocks = <&clks IMX6SX_CLK_USDHC1>,
877                                          <&clks IMX6SX_CLK_USDHC1>,
878                                          <&clks IMX6SX_CLK_USDHC1>;
879                                 clock-names = "ipg", "ahb", "per";
880                                 bus-width = <4>;
881                                 status = "disabled";
882                         };
883
884                         usdhc2: usdhc@02194000 {
885                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
886                                 reg = <0x02194000 0x4000>;
887                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
888                                 clocks = <&clks IMX6SX_CLK_USDHC2>,
889                                          <&clks IMX6SX_CLK_USDHC2>,
890                                          <&clks IMX6SX_CLK_USDHC2>;
891                                 clock-names = "ipg", "ahb", "per";
892                                 bus-width = <4>;
893                                 status = "disabled";
894                         };
895
896                         usdhc3: usdhc@02198000 {
897                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
898                                 reg = <0x02198000 0x4000>;
899                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
900                                 clocks = <&clks IMX6SX_CLK_USDHC3>,
901                                          <&clks IMX6SX_CLK_USDHC3>,
902                                          <&clks IMX6SX_CLK_USDHC3>;
903                                 clock-names = "ipg", "ahb", "per";
904                                 bus-width = <4>;
905                                 status = "disabled";
906                         };
907
908                         usdhc4: usdhc@0219c000 {
909                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
910                                 reg = <0x0219c000 0x4000>;
911                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
912                                 clocks = <&clks IMX6SX_CLK_USDHC4>,
913                                          <&clks IMX6SX_CLK_USDHC4>,
914                                          <&clks IMX6SX_CLK_USDHC4>;
915                                 clock-names = "ipg", "ahb", "per";
916                                 bus-width = <4>;
917                                 status = "disabled";
918                         };
919
920                         i2c1: i2c@021a0000 {
921                                 #address-cells = <1>;
922                                 #size-cells = <0>;
923                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
924                                 reg = <0x021a0000 0x4000>;
925                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
926                                 clocks = <&clks IMX6SX_CLK_I2C1>;
927                                 status = "disabled";
928                         };
929
930                         i2c2: i2c@021a4000 {
931                                 #address-cells = <1>;
932                                 #size-cells = <0>;
933                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
934                                 reg = <0x021a4000 0x4000>;
935                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
936                                 clocks = <&clks IMX6SX_CLK_I2C2>;
937                                 status = "disabled";
938                         };
939
940                         i2c3: i2c@021a8000 {
941                                 #address-cells = <1>;
942                                 #size-cells = <0>;
943                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
944                                 reg = <0x021a8000 0x4000>;
945                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
946                                 clocks = <&clks IMX6SX_CLK_I2C3>;
947                                 status = "disabled";
948                         };
949
950                         mmdc: mmdc@021b0000 {
951                                 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
952                                 reg = <0x021b0000 0x4000>;
953                         };
954
955                         fec2: ethernet@021b4000 {
956                                 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
957                                 reg = <0x021b4000 0x4000>;
958                                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
959                                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
960                                 clocks = <&clks IMX6SX_CLK_ENET>,
961                                          <&clks IMX6SX_CLK_ENET_AHB>,
962                                          <&clks IMX6SX_CLK_ENET_PTP>,
963                                          <&clks IMX6SX_CLK_ENET2_REF_125M>,
964                                          <&clks IMX6SX_CLK_ENET_PTP>;
965                                 clock-names = "ipg", "ahb", "ptp",
966                                               "enet_clk_ref", "enet_out";
967                                 status = "disabled";
968                         };
969
970                         weim: weim@021b8000 {
971                                 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
972                                 reg = <0x021b8000 0x4000>;
973                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
974                                 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
975                         };
976
977                         ocotp: ocotp@021bc000 {
978                                 compatible = "fsl,imx6sx-ocotp", "syscon";
979                                 reg = <0x021bc000 0x4000>;
980                                 clocks = <&clks IMX6SX_CLK_OCOTP>;
981                         };
982
983                         sai1: sai@021d4000 {
984                                 compatible = "fsl,imx6sx-sai";
985                                 reg = <0x021d4000 0x4000>;
986                                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
987                                 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
988                                          <&clks IMX6SX_CLK_SAI1>,
989                                          <&clks 0>, <&clks 0>;
990                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
991                                 dma-names = "rx", "tx";
992                                 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
993                                 status = "disabled";
994                         };
995
996                         audmux: audmux@021d8000 {
997                                 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
998                                 reg = <0x021d8000 0x4000>;
999                                 status = "disabled";
1000                         };
1001
1002                         sai2: sai@021dc000 {
1003                                 compatible = "fsl,imx6sx-sai";
1004                                 reg = <0x021dc000 0x4000>;
1005                                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1006                                 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
1007                                          <&clks IMX6SX_CLK_SAI2>,
1008                                          <&clks 0>, <&clks 0>;
1009                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1010                                 dma-names = "rx", "tx";
1011                                 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
1012                                 status = "disabled";
1013                         };
1014
1015                         qspi1: qspi@021e0000 {
1016                                 #address-cells = <1>;
1017                                 #size-cells = <0>;
1018                                 compatible = "fsl,imx6sx-qspi";
1019                                 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1020                                 reg-names = "QuadSPI", "QuadSPI-memory";
1021                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1022                                 clocks = <&clks IMX6SX_CLK_QSPI1>,
1023                                          <&clks IMX6SX_CLK_QSPI1>;
1024                                 clock-names = "qspi_en", "qspi";
1025                                 status = "disabled";
1026                         };
1027
1028                         qspi2: qspi@021e4000 {
1029                                 #address-cells = <1>;
1030                                 #size-cells = <0>;
1031                                 compatible = "fsl,imx6sx-qspi";
1032                                 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1033                                 reg-names = "QuadSPI", "QuadSPI-memory";
1034                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1035                                 clocks = <&clks IMX6SX_CLK_QSPI2>,
1036                                          <&clks IMX6SX_CLK_QSPI2>;
1037                                 clock-names = "qspi_en", "qspi";
1038                                 status = "disabled";
1039                         };
1040
1041                         uart2: serial@021e8000 {
1042                                 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1043                                 reg = <0x021e8000 0x4000>;
1044                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1045                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1046                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1047                                 clock-names = "ipg", "per";
1048                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1049                                 dma-names = "rx", "tx";
1050                                 status = "disabled";
1051                         };
1052
1053                         uart3: serial@021ec000 {
1054                                 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1055                                 reg = <0x021ec000 0x4000>;
1056                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1057                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1058                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1059                                 clock-names = "ipg", "per";
1060                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1061                                 dma-names = "rx", "tx";
1062                                 status = "disabled";
1063                         };
1064
1065                         uart4: serial@021f0000 {
1066                                 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1067                                 reg = <0x021f0000 0x4000>;
1068                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1069                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1070                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1071                                 clock-names = "ipg", "per";
1072                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1073                                 dma-names = "rx", "tx";
1074                                 status = "disabled";
1075                         };
1076
1077                         uart5: serial@021f4000 {
1078                                 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1079                                 reg = <0x021f4000 0x4000>;
1080                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1081                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1082                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1083                                 clock-names = "ipg", "per";
1084                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1085                                 dma-names = "rx", "tx";
1086                                 status = "disabled";
1087                         };
1088
1089                         i2c4: i2c@021f8000 {
1090                                 #address-cells = <1>;
1091                                 #size-cells = <0>;
1092                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1093                                 reg = <0x021f8000 0x4000>;
1094                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1095                                 clocks = <&clks IMX6SX_CLK_I2C4>;
1096                                 status = "disabled";
1097                         };
1098                 };
1099
1100                 aips3: aips-bus@02200000 {
1101                         compatible = "fsl,aips-bus", "simple-bus";
1102                         #address-cells = <1>;
1103                         #size-cells = <1>;
1104                         reg = <0x02200000 0x100000>;
1105                         ranges;
1106
1107                         spba-bus@02200000 {
1108                                 compatible = "fsl,spba-bus", "simple-bus";
1109                                 #address-cells = <1>;
1110                                 #size-cells = <1>;
1111                                 reg = <0x02240000 0x40000>;
1112                                 ranges;
1113
1114                                 csi1: csi@02214000 {
1115                                         reg = <0x02214000 0x4000>;
1116                                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1117                                         clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1118                                                  <&clks IMX6SX_CLK_CSI>,
1119                                                  <&clks IMX6SX_CLK_DCIC1>;
1120                                         clock-names = "disp-axi", "csi_mclk", "dcic";
1121                                         status = "disabled";
1122                                 };
1123
1124                                 pxp: pxp@02218000 {
1125                                         reg = <0x02218000 0x4000>;
1126                                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1127                                         clocks = <&clks IMX6SX_CLK_PXP_AXI>,
1128                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1129                                         clock-names = "pxp-axi", "disp-axi";
1130                                         status = "disabled";
1131                                 };
1132
1133                                 csi2: csi@0221c000 {
1134                                         reg = <0x0221c000 0x4000>;
1135                                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1136                                         clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1137                                                  <&clks IMX6SX_CLK_CSI>,
1138                                                  <&clks IMX6SX_CLK_DCIC2>;
1139                                         clock-names = "disp-axi", "csi_mclk", "dcic";
1140                                         status = "disabled";
1141                                 };
1142
1143                                 lcdif1: lcdif@02220000 {
1144                                         compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1145                                         reg = <0x02220000 0x4000>;
1146                                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1147                                         clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1148                                                  <&clks IMX6SX_CLK_LCDIF_APB>,
1149                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1150                                         clock-names = "pix", "axi", "disp_axi";
1151                                         status = "disabled";
1152                                 };
1153
1154                                 lcdif2: lcdif@02224000 {
1155                                         compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1156                                         reg = <0x02224000 0x4000>;
1157                                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1158                                         clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1159                                                  <&clks IMX6SX_CLK_LCDIF_APB>,
1160                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1161                                         clock-names = "pix", "axi", "disp_axi";
1162                                         status = "disabled";
1163                                 };
1164
1165                                 vadc: vadc@02228000 {
1166                                         reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1167                                         reg-names = "vadc-vafe", "vadc-vdec";
1168                                         clocks = <&clks IMX6SX_CLK_VADC>,
1169                                                  <&clks IMX6SX_CLK_CSI>;
1170                                         clock-names = "vadc", "csi";
1171                                         status = "disabled";
1172                                 };
1173                         };
1174
1175                         adc1: adc@02280000 {
1176                                 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1177                                 reg = <0x02280000 0x4000>;
1178                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1179                                 clocks = <&clks IMX6SX_CLK_IPG>;
1180                                 clock-names = "adc";
1181                                 fsl,adck-max-frequency = <30000000>, <40000000>,
1182                                                          <20000000>;
1183                                 status = "disabled";
1184                         };
1185
1186                         adc2: adc@02284000 {
1187                                 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1188                                 reg = <0x02284000 0x4000>;
1189                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1190                                 clocks = <&clks IMX6SX_CLK_IPG>;
1191                                 clock-names = "adc";
1192                                 fsl,adck-max-frequency = <30000000>, <40000000>,
1193                                                          <20000000>;
1194                                 status = "disabled";
1195                         };
1196
1197                         wdog3: wdog@02288000 {
1198                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1199                                 reg = <0x02288000 0x4000>;
1200                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1201                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
1202                                 status = "disabled";
1203                         };
1204
1205                         ecspi5: ecspi@0228c000 {
1206                                 #address-cells = <1>;
1207                                 #size-cells = <0>;
1208                                 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1209                                 reg = <0x0228c000 0x4000>;
1210                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1211                                 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1212                                          <&clks IMX6SX_CLK_ECSPI5>;
1213                                 clock-names = "ipg", "per";
1214                                 status = "disabled";
1215                         };
1216
1217                         uart6: serial@022a0000 {
1218                                 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1219                                 reg = <0x022a0000 0x4000>;
1220                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1221                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1222                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1223                                 clock-names = "ipg", "per";
1224                                 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1225                                 dma-names = "rx", "tx";
1226                                 status = "disabled";
1227                         };
1228
1229                         pwm5: pwm@022a4000 {
1230                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1231                                 reg = <0x022a4000 0x4000>;
1232                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1233                                 clocks = <&clks IMX6SX_CLK_PWM5>,
1234                                          <&clks IMX6SX_CLK_PWM5>;
1235                                 clock-names = "ipg", "per";
1236                                 #pwm-cells = <2>;
1237                         };
1238
1239                         pwm6: pwm@022a8000 {
1240                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1241                                 reg = <0x022a8000 0x4000>;
1242                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1243                                 clocks = <&clks IMX6SX_CLK_PWM6>,
1244                                          <&clks IMX6SX_CLK_PWM6>;
1245                                 clock-names = "ipg", "per";
1246                                 #pwm-cells = <2>;
1247                         };
1248
1249                         pwm7: pwm@022ac000 {
1250                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1251                                 reg = <0x022ac000 0x4000>;
1252                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1253                                 clocks = <&clks IMX6SX_CLK_PWM7>,
1254                                          <&clks IMX6SX_CLK_PWM7>;
1255                                 clock-names = "ipg", "per";
1256                                 #pwm-cells = <2>;
1257                         };
1258
1259                         pwm8: pwm@0022b0000 {
1260                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1261                                 reg = <0x0022b0000 0x4000>;
1262                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1263                                 clocks = <&clks IMX6SX_CLK_PWM8>,
1264                                          <&clks IMX6SX_CLK_PWM8>;
1265                                 clock-names = "ipg", "per";
1266                                 #pwm-cells = <2>;
1267                         };
1268                 };
1269
1270                 pcie: pcie@0x08000000 {
1271                         compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1272                         reg = <0x08ffc000 0x4000>; /* DBI */
1273                         #address-cells = <3>;
1274                         #size-cells = <2>;
1275                         device_type = "pci";
1276                                   /* configuration space */
1277                         ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000
1278                                   /* downstream I/O */
1279                                   0x81000000 0 0          0x08f80000 0 0x00010000
1280                                   /* non-prefetchable memory */
1281                                   0x82000000 0 0x08000000 0x08000000 0 0x00f00000>;
1282                         num-lanes = <1>;
1283                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1284                         clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>,
1285                                  <&clks IMX6SX_CLK_PCIE_AXI>,
1286                                  <&clks IMX6SX_CLK_LVDS1_OUT>,
1287                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1288                         clock-names = "pcie_ref_125m", "pcie_axi",
1289                                       "lvds_gate", "display_axi";
1290                         status = "disabled";
1291                 };
1292         };
1293
1294         gpu-subsystem {
1295                 compatible = "fsl,imx-gpu-subsystem";
1296                 cores = <&gpu>;
1297         };
1298 };