1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright 2011 Freescale Semiconductor, Inc.
4 // Copyright 2011 Linaro Ltd.
6 #include <dt-bindings/clock/imx6qdl-clock.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 * The decompressor and also some bootloaders rely on a
14 * pre-existing /chosen node to be available to insert the
15 * command line and merge other ATAGS info.
16 * Also for U-Boot there must be a pre-existing /memory node.
19 memory { device_type = "memory"; };
55 compatible = "fsl,imx-ckil", "fixed-clock";
57 clock-frequency = <32768>;
61 compatible = "fsl,imx-ckih1", "fixed-clock";
63 clock-frequency = <0>;
67 compatible = "fsl,imx-osc", "fixed-clock";
69 clock-frequency = <24000000>;
74 compatible = "fsl,imx6q-tempmon";
75 interrupt-parent = <&gpc>;
76 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
77 fsl,tempmon = <&anatop>;
78 fsl,tempmon-data = <&ocotp>;
79 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
85 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
98 lvds0_mux_0: endpoint {
99 remote-endpoint = <&ipu1_di0_lvds0>;
106 lvds0_mux_1: endpoint {
107 remote-endpoint = <&ipu1_di1_lvds0>;
113 #address-cells = <1>;
121 lvds1_mux_0: endpoint {
122 remote-endpoint = <&ipu1_di0_lvds1>;
129 lvds1_mux_1: endpoint {
130 remote-endpoint = <&ipu1_di1_lvds1>;
137 compatible = "arm,cortex-a9-pmu";
138 interrupt-parent = <&gpc>;
139 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
143 #address-cells = <1>;
145 compatible = "simple-bus";
146 interrupt-parent = <&gpc>;
150 dma_apbh: dma-apbh@110000 {
151 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
152 reg = <0x00110000 0x2000>;
153 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
154 <0 13 IRQ_TYPE_LEVEL_HIGH>,
155 <0 13 IRQ_TYPE_LEVEL_HIGH>,
156 <0 13 IRQ_TYPE_LEVEL_HIGH>;
157 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
160 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
163 gpmi: gpmi-nand@112000 {
164 compatible = "fsl,imx6q-gpmi-nand";
165 #address-cells = <1>;
167 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
168 reg-names = "gpmi-nand", "bch";
169 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
170 interrupt-names = "bch";
171 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
172 <&clks IMX6QDL_CLK_GPMI_APB>,
173 <&clks IMX6QDL_CLK_GPMI_BCH>,
174 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
175 <&clks IMX6QDL_CLK_PER1_BCH>;
176 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
177 "gpmi_bch_apb", "per1_bch";
178 dmas = <&dma_apbh 0>;
184 #address-cells = <1>;
186 reg = <0x00120000 0x9000>;
187 interrupts = <0 115 0x04>;
189 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
190 <&clks IMX6QDL_CLK_HDMI_ISFR>;
191 clock-names = "iahb", "isfr";
197 hdmi_mux_0: endpoint {
198 remote-endpoint = <&ipu1_di0_hdmi>;
205 hdmi_mux_1: endpoint {
206 remote-endpoint = <&ipu1_di1_hdmi>;
212 compatible = "vivante,gc";
213 reg = <0x00130000 0x4000>;
214 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
216 <&clks IMX6QDL_CLK_GPU3D_CORE>,
217 <&clks IMX6QDL_CLK_GPU3D_SHADER>;
218 clock-names = "bus", "core", "shader";
219 power-domains = <&pd_pu>;
223 compatible = "vivante,gc";
224 reg = <0x00134000 0x4000>;
225 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
227 <&clks IMX6QDL_CLK_GPU2D_CORE>;
228 clock-names = "bus", "core";
229 power-domains = <&pd_pu>;
233 compatible = "arm,cortex-a9-twd-timer";
234 reg = <0x00a00600 0x20>;
235 interrupts = <1 13 0xf01>;
236 interrupt-parent = <&intc>;
237 clocks = <&clks IMX6QDL_CLK_TWD>;
240 intc: interrupt-controller@a01000 {
241 compatible = "arm,cortex-a9-gic";
242 #interrupt-cells = <3>;
243 interrupt-controller;
244 reg = <0x00a01000 0x1000>,
246 interrupt-parent = <&intc>;
249 L2: l2-cache@a02000 {
250 compatible = "arm,pl310-cache";
251 reg = <0x00a02000 0x1000>;
252 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
255 arm,tag-latency = <4 2 3>;
256 arm,data-latency = <4 2 3>;
261 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
262 reg = <0x01ffc000 0x04000>,
263 <0x01f00000 0x80000>;
264 reg-names = "dbi", "config";
265 #address-cells = <3>;
268 bus-range = <0x00 0xff>;
269 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
270 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
272 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
273 interrupt-names = "msi";
274 #interrupt-cells = <1>;
275 interrupt-map-mask = <0 0 0 0x7>;
276 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
277 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
278 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
279 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
281 <&clks IMX6QDL_CLK_LVDS1_GATE>,
282 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
283 clock-names = "pcie", "pcie_bus", "pcie_phy";
287 aips-bus@2000000 { /* AIPS1 */
288 compatible = "fsl,aips-bus", "simple-bus";
289 #address-cells = <1>;
291 reg = <0x02000000 0x100000>;
295 compatible = "fsl,spba-bus", "simple-bus";
296 #address-cells = <1>;
298 reg = <0x02000000 0x40000>;
301 spdif: spdif@2004000 {
302 compatible = "fsl,imx35-spdif";
303 reg = <0x02004000 0x4000>;
304 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
305 dmas = <&sdma 14 18 0>,
307 dma-names = "rx", "tx";
308 clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
309 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
310 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
311 <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
312 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
313 clock-names = "core", "rxtx0",
321 ecspi1: spi@2008000 {
322 #address-cells = <1>;
324 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
325 reg = <0x02008000 0x4000>;
326 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
327 clocks = <&clks IMX6QDL_CLK_ECSPI1>,
328 <&clks IMX6QDL_CLK_ECSPI1>;
329 clock-names = "ipg", "per";
330 dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
331 dma-names = "rx", "tx";
335 ecspi2: spi@200c000 {
336 #address-cells = <1>;
338 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
339 reg = <0x0200c000 0x4000>;
340 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&clks IMX6QDL_CLK_ECSPI2>,
342 <&clks IMX6QDL_CLK_ECSPI2>;
343 clock-names = "ipg", "per";
344 dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
345 dma-names = "rx", "tx";
349 ecspi3: spi@2010000 {
350 #address-cells = <1>;
352 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
353 reg = <0x02010000 0x4000>;
354 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&clks IMX6QDL_CLK_ECSPI3>,
356 <&clks IMX6QDL_CLK_ECSPI3>;
357 clock-names = "ipg", "per";
358 dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
359 dma-names = "rx", "tx";
363 ecspi4: spi@2014000 {
364 #address-cells = <1>;
366 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
367 reg = <0x02014000 0x4000>;
368 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&clks IMX6QDL_CLK_ECSPI4>,
370 <&clks IMX6QDL_CLK_ECSPI4>;
371 clock-names = "ipg", "per";
372 dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
373 dma-names = "rx", "tx";
377 uart1: serial@2020000 {
378 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
379 reg = <0x02020000 0x4000>;
380 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
382 <&clks IMX6QDL_CLK_UART_SERIAL>;
383 clock-names = "ipg", "per";
384 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
385 dma-names = "rx", "tx";
390 #sound-dai-cells = <0>;
391 compatible = "fsl,imx35-esai";
392 reg = <0x02024000 0x4000>;
393 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
394 clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
395 <&clks IMX6QDL_CLK_ESAI_MEM>,
396 <&clks IMX6QDL_CLK_ESAI_EXTAL>,
397 <&clks IMX6QDL_CLK_ESAI_IPG>,
398 <&clks IMX6QDL_CLK_SPBA>;
399 clock-names = "core", "mem", "extal", "fsys", "spba";
400 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
401 dma-names = "rx", "tx";
406 #sound-dai-cells = <0>;
407 compatible = "fsl,imx6q-ssi",
409 reg = <0x02028000 0x4000>;
410 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
411 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
412 <&clks IMX6QDL_CLK_SSI1>;
413 clock-names = "ipg", "baud";
414 dmas = <&sdma 37 1 0>,
416 dma-names = "rx", "tx";
417 fsl,fifo-depth = <15>;
422 #sound-dai-cells = <0>;
423 compatible = "fsl,imx6q-ssi",
425 reg = <0x0202c000 0x4000>;
426 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
428 <&clks IMX6QDL_CLK_SSI2>;
429 clock-names = "ipg", "baud";
430 dmas = <&sdma 41 1 0>,
432 dma-names = "rx", "tx";
433 fsl,fifo-depth = <15>;
438 #sound-dai-cells = <0>;
439 compatible = "fsl,imx6q-ssi",
441 reg = <0x02030000 0x4000>;
442 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
444 <&clks IMX6QDL_CLK_SSI3>;
445 clock-names = "ipg", "baud";
446 dmas = <&sdma 45 1 0>,
448 dma-names = "rx", "tx";
449 fsl,fifo-depth = <15>;
454 compatible = "fsl,imx53-asrc";
455 reg = <0x02034000 0x4000>;
456 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
458 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
459 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
460 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
461 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
462 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
463 <&clks IMX6QDL_CLK_SPBA>;
464 clock-names = "mem", "ipg", "asrck_0",
465 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
466 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
467 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
468 "asrck_d", "asrck_e", "asrck_f", "spba";
469 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
470 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
471 dma-names = "rxa", "rxb", "rxc",
473 fsl,asrc-rate = <48000>;
474 fsl,asrc-width = <16>;
479 reg = <0x0203c000 0x4000>;
484 compatible = "cnm,coda960";
485 reg = <0x02040000 0x3c000>;
486 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
487 <0 3 IRQ_TYPE_LEVEL_HIGH>;
488 interrupt-names = "bit", "jpeg";
489 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
490 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
491 clock-names = "per", "ahb";
492 power-domains = <&pd_pu>;
497 aipstz@207c000 { /* AIPSTZ1 */
498 reg = <0x0207c000 0x4000>;
503 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
504 reg = <0x02080000 0x4000>;
505 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
506 clocks = <&clks IMX6QDL_CLK_IPG>,
507 <&clks IMX6QDL_CLK_PWM1>;
508 clock-names = "ipg", "per";
514 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
515 reg = <0x02084000 0x4000>;
516 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&clks IMX6QDL_CLK_IPG>,
518 <&clks IMX6QDL_CLK_PWM2>;
519 clock-names = "ipg", "per";
525 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
526 reg = <0x02088000 0x4000>;
527 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
528 clocks = <&clks IMX6QDL_CLK_IPG>,
529 <&clks IMX6QDL_CLK_PWM3>;
530 clock-names = "ipg", "per";
536 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
537 reg = <0x0208c000 0x4000>;
538 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
539 clocks = <&clks IMX6QDL_CLK_IPG>,
540 <&clks IMX6QDL_CLK_PWM4>;
541 clock-names = "ipg", "per";
545 can1: flexcan@2090000 {
546 compatible = "fsl,imx6q-flexcan";
547 reg = <0x02090000 0x4000>;
548 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
549 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
550 <&clks IMX6QDL_CLK_CAN1_SERIAL>;
551 clock-names = "ipg", "per";
555 can2: flexcan@2094000 {
556 compatible = "fsl,imx6q-flexcan";
557 reg = <0x02094000 0x4000>;
558 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
560 <&clks IMX6QDL_CLK_CAN2_SERIAL>;
561 clock-names = "ipg", "per";
566 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
567 reg = <0x02098000 0x4000>;
568 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
569 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
570 <&clks IMX6QDL_CLK_GPT_IPG_PER>,
571 <&clks IMX6QDL_CLK_GPT_3M>;
572 clock-names = "ipg", "per", "osc_per";
575 gpio1: gpio@209c000 {
576 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
577 reg = <0x0209c000 0x4000>;
578 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
579 <0 67 IRQ_TYPE_LEVEL_HIGH>;
582 interrupt-controller;
583 #interrupt-cells = <2>;
586 gpio2: gpio@20a0000 {
587 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
588 reg = <0x020a0000 0x4000>;
589 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
590 <0 69 IRQ_TYPE_LEVEL_HIGH>;
593 interrupt-controller;
594 #interrupt-cells = <2>;
597 gpio3: gpio@20a4000 {
598 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
599 reg = <0x020a4000 0x4000>;
600 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
601 <0 71 IRQ_TYPE_LEVEL_HIGH>;
604 interrupt-controller;
605 #interrupt-cells = <2>;
608 gpio4: gpio@20a8000 {
609 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
610 reg = <0x020a8000 0x4000>;
611 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
612 <0 73 IRQ_TYPE_LEVEL_HIGH>;
615 interrupt-controller;
616 #interrupt-cells = <2>;
619 gpio5: gpio@20ac000 {
620 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
621 reg = <0x020ac000 0x4000>;
622 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
623 <0 75 IRQ_TYPE_LEVEL_HIGH>;
626 interrupt-controller;
627 #interrupt-cells = <2>;
630 gpio6: gpio@20b0000 {
631 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
632 reg = <0x020b0000 0x4000>;
633 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
634 <0 77 IRQ_TYPE_LEVEL_HIGH>;
637 interrupt-controller;
638 #interrupt-cells = <2>;
641 gpio7: gpio@20b4000 {
642 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
643 reg = <0x020b4000 0x4000>;
644 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
645 <0 79 IRQ_TYPE_LEVEL_HIGH>;
648 interrupt-controller;
649 #interrupt-cells = <2>;
653 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
654 reg = <0x020b8000 0x4000>;
655 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&clks IMX6QDL_CLK_IPG>;
660 wdog1: wdog@20bc000 {
661 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
662 reg = <0x020bc000 0x4000>;
663 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
664 clocks = <&clks IMX6QDL_CLK_DUMMY>;
667 wdog2: wdog@20c0000 {
668 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
669 reg = <0x020c0000 0x4000>;
670 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
671 clocks = <&clks IMX6QDL_CLK_DUMMY>;
676 compatible = "fsl,imx6q-ccm";
677 reg = <0x020c4000 0x4000>;
678 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
679 <0 88 IRQ_TYPE_LEVEL_HIGH>;
683 anatop: anatop@20c8000 {
684 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
685 reg = <0x020c8000 0x1000>;
686 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
687 <0 54 IRQ_TYPE_LEVEL_HIGH>,
688 <0 127 IRQ_TYPE_LEVEL_HIGH>;
691 compatible = "fsl,anatop-regulator";
692 regulator-name = "vdd1p1";
693 regulator-min-microvolt = <1000000>;
694 regulator-max-microvolt = <1200000>;
696 anatop-reg-offset = <0x110>;
697 anatop-vol-bit-shift = <8>;
698 anatop-vol-bit-width = <5>;
699 anatop-min-bit-val = <4>;
700 anatop-min-voltage = <800000>;
701 anatop-max-voltage = <1375000>;
702 anatop-enable-bit = <0>;
706 compatible = "fsl,anatop-regulator";
707 regulator-name = "vdd3p0";
708 regulator-min-microvolt = <2800000>;
709 regulator-max-microvolt = <3150000>;
711 anatop-reg-offset = <0x120>;
712 anatop-vol-bit-shift = <8>;
713 anatop-vol-bit-width = <5>;
714 anatop-min-bit-val = <0>;
715 anatop-min-voltage = <2625000>;
716 anatop-max-voltage = <3400000>;
717 anatop-enable-bit = <0>;
721 compatible = "fsl,anatop-regulator";
722 regulator-name = "vdd2p5";
723 regulator-min-microvolt = <2250000>;
724 regulator-max-microvolt = <2750000>;
726 anatop-reg-offset = <0x130>;
727 anatop-vol-bit-shift = <8>;
728 anatop-vol-bit-width = <5>;
729 anatop-min-bit-val = <0>;
730 anatop-min-voltage = <2100000>;
731 anatop-max-voltage = <2875000>;
732 anatop-enable-bit = <0>;
735 reg_arm: regulator-vddcore {
736 compatible = "fsl,anatop-regulator";
737 regulator-name = "vddarm";
738 regulator-min-microvolt = <725000>;
739 regulator-max-microvolt = <1450000>;
741 anatop-reg-offset = <0x140>;
742 anatop-vol-bit-shift = <0>;
743 anatop-vol-bit-width = <5>;
744 anatop-delay-reg-offset = <0x170>;
745 anatop-delay-bit-shift = <24>;
746 anatop-delay-bit-width = <2>;
747 anatop-min-bit-val = <1>;
748 anatop-min-voltage = <725000>;
749 anatop-max-voltage = <1450000>;
752 reg_pu: regulator-vddpu {
753 compatible = "fsl,anatop-regulator";
754 regulator-name = "vddpu";
755 regulator-min-microvolt = <725000>;
756 regulator-max-microvolt = <1450000>;
757 regulator-enable-ramp-delay = <150>;
758 anatop-reg-offset = <0x140>;
759 anatop-vol-bit-shift = <9>;
760 anatop-vol-bit-width = <5>;
761 anatop-delay-reg-offset = <0x170>;
762 anatop-delay-bit-shift = <26>;
763 anatop-delay-bit-width = <2>;
764 anatop-min-bit-val = <1>;
765 anatop-min-voltage = <725000>;
766 anatop-max-voltage = <1450000>;
769 reg_soc: regulator-vddsoc {
770 compatible = "fsl,anatop-regulator";
771 regulator-name = "vddsoc";
772 regulator-min-microvolt = <725000>;
773 regulator-max-microvolt = <1450000>;
775 anatop-reg-offset = <0x140>;
776 anatop-vol-bit-shift = <18>;
777 anatop-vol-bit-width = <5>;
778 anatop-delay-reg-offset = <0x170>;
779 anatop-delay-bit-shift = <28>;
780 anatop-delay-bit-width = <2>;
781 anatop-min-bit-val = <1>;
782 anatop-min-voltage = <725000>;
783 anatop-max-voltage = <1450000>;
787 usbphy1: usbphy@20c9000 {
788 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
789 reg = <0x020c9000 0x1000>;
790 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
791 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
792 fsl,anatop = <&anatop>;
795 usbphy2: usbphy@20ca000 {
796 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
797 reg = <0x020ca000 0x1000>;
798 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
799 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
800 fsl,anatop = <&anatop>;
804 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
805 reg = <0x020cc000 0x4000>;
807 snvs_rtc: snvs-rtc-lp {
808 compatible = "fsl,sec-v4.0-mon-rtc-lp";
811 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
812 <0 20 IRQ_TYPE_LEVEL_HIGH>;
815 snvs_poweroff: snvs-poweroff {
816 compatible = "syscon-poweroff";
824 snvs_lpgpr: snvs-lpgpr {
825 compatible = "fsl,imx6q-snvs-lpgpr";
829 epit1: epit@20d0000 { /* EPIT1 */
830 reg = <0x020d0000 0x4000>;
831 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
834 epit2: epit@20d4000 { /* EPIT2 */
835 reg = <0x020d4000 0x4000>;
836 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
840 compatible = "fsl,imx6q-src", "fsl,imx51-src";
841 reg = <0x020d8000 0x4000>;
842 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
843 <0 96 IRQ_TYPE_LEVEL_HIGH>;
848 compatible = "fsl,imx6q-gpc";
849 reg = <0x020dc000 0x4000>;
850 interrupt-controller;
851 #interrupt-cells = <3>;
852 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
853 <0 90 IRQ_TYPE_LEVEL_HIGH>;
854 interrupt-parent = <&intc>;
855 clocks = <&clks IMX6QDL_CLK_IPG>;
859 #address-cells = <1>;
864 #power-domain-cells = <0>;
866 pd_pu: power-domain@1 {
868 #power-domain-cells = <0>;
869 power-supply = <®_pu>;
870 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
871 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
872 <&clks IMX6QDL_CLK_GPU2D_CORE>,
873 <&clks IMX6QDL_CLK_GPU2D_AXI>,
874 <&clks IMX6QDL_CLK_OPENVG_AXI>,
875 <&clks IMX6QDL_CLK_VPU_AXI>;
880 gpr: iomuxc-gpr@20e0000 {
881 compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
882 reg = <0x20e0000 0x38>;
884 mux: mux-controller {
885 compatible = "mmio-mux";
886 #mux-control-cells = <1>;
890 iomuxc: iomuxc@20e0000 {
891 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
892 reg = <0x20e0000 0x4000>;
895 dcic1: dcic@20e4000 {
896 reg = <0x020e4000 0x4000>;
897 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
900 dcic2: dcic@20e8000 {
901 reg = <0x020e8000 0x4000>;
902 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
906 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
907 reg = <0x020ec000 0x4000>;
908 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
909 clocks = <&clks IMX6QDL_CLK_SDMA>,
910 <&clks IMX6QDL_CLK_SDMA>;
911 clock-names = "ipg", "ahb";
913 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
917 aips-bus@2100000 { /* AIPS2 */
918 compatible = "fsl,aips-bus", "simple-bus";
919 #address-cells = <1>;
921 reg = <0x02100000 0x100000>;
924 crypto: caam@2100000 {
925 compatible = "fsl,sec-v4.0";
926 #address-cells = <1>;
928 reg = <0x2100000 0x10000>;
929 ranges = <0 0x2100000 0x10000>;
930 clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
931 <&clks IMX6QDL_CLK_CAAM_ACLK>,
932 <&clks IMX6QDL_CLK_CAAM_IPG>,
933 <&clks IMX6QDL_CLK_EIM_SLOW>;
934 clock-names = "mem", "aclk", "ipg", "emi_slow";
937 compatible = "fsl,sec-v4.0-job-ring";
938 reg = <0x1000 0x1000>;
939 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
943 compatible = "fsl,sec-v4.0-job-ring";
944 reg = <0x2000 0x1000>;
945 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
949 aipstz@217c000 { /* AIPSTZ2 */
950 reg = <0x0217c000 0x4000>;
953 usbotg: usb@2184000 {
954 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
955 reg = <0x02184000 0x200>;
956 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
957 clocks = <&clks IMX6QDL_CLK_USBOH3>;
958 fsl,usbphy = <&usbphy1>;
959 fsl,usbmisc = <&usbmisc 0>;
960 ahb-burst-config = <0x0>;
961 tx-burst-size-dword = <0x10>;
962 rx-burst-size-dword = <0x10>;
967 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
968 reg = <0x02184200 0x200>;
969 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
970 clocks = <&clks IMX6QDL_CLK_USBOH3>;
971 fsl,usbphy = <&usbphy2>;
972 fsl,usbmisc = <&usbmisc 1>;
974 ahb-burst-config = <0x0>;
975 tx-burst-size-dword = <0x10>;
976 rx-burst-size-dword = <0x10>;
981 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
982 reg = <0x02184400 0x200>;
983 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
984 clocks = <&clks IMX6QDL_CLK_USBOH3>;
985 fsl,usbmisc = <&usbmisc 2>;
987 ahb-burst-config = <0x0>;
988 tx-burst-size-dword = <0x10>;
989 rx-burst-size-dword = <0x10>;
994 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
995 reg = <0x02184600 0x200>;
996 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
997 clocks = <&clks IMX6QDL_CLK_USBOH3>;
998 fsl,usbmisc = <&usbmisc 3>;
1000 ahb-burst-config = <0x0>;
1001 tx-burst-size-dword = <0x10>;
1002 rx-burst-size-dword = <0x10>;
1003 status = "disabled";
1006 usbmisc: usbmisc@2184800 {
1008 compatible = "fsl,imx6q-usbmisc";
1009 reg = <0x02184800 0x200>;
1010 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1013 fec: ethernet@2188000 {
1014 compatible = "fsl,imx6q-fec";
1015 reg = <0x02188000 0x4000>;
1016 interrupt-names = "int0", "pps";
1017 interrupts-extended =
1018 <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
1019 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
1020 clocks = <&clks IMX6QDL_CLK_ENET>,
1021 <&clks IMX6QDL_CLK_ENET>,
1022 <&clks IMX6QDL_CLK_ENET_REF>;
1023 clock-names = "ipg", "ahb", "ptp";
1024 status = "disabled";
1028 reg = <0x0218c000 0x4000>;
1029 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
1030 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1031 <0 126 IRQ_TYPE_LEVEL_HIGH>;
1034 usdhc1: usdhc@2190000 {
1035 compatible = "fsl,imx6q-usdhc";
1036 reg = <0x02190000 0x4000>;
1037 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
1038 clocks = <&clks IMX6QDL_CLK_USDHC1>,
1039 <&clks IMX6QDL_CLK_USDHC1>,
1040 <&clks IMX6QDL_CLK_USDHC1>;
1041 clock-names = "ipg", "ahb", "per";
1043 status = "disabled";
1046 usdhc2: usdhc@2194000 {
1047 compatible = "fsl,imx6q-usdhc";
1048 reg = <0x02194000 0x4000>;
1049 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
1050 clocks = <&clks IMX6QDL_CLK_USDHC2>,
1051 <&clks IMX6QDL_CLK_USDHC2>,
1052 <&clks IMX6QDL_CLK_USDHC2>;
1053 clock-names = "ipg", "ahb", "per";
1055 status = "disabled";
1058 usdhc3: usdhc@2198000 {
1059 compatible = "fsl,imx6q-usdhc";
1060 reg = <0x02198000 0x4000>;
1061 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
1062 clocks = <&clks IMX6QDL_CLK_USDHC3>,
1063 <&clks IMX6QDL_CLK_USDHC3>,
1064 <&clks IMX6QDL_CLK_USDHC3>;
1065 clock-names = "ipg", "ahb", "per";
1067 status = "disabled";
1070 usdhc4: usdhc@219c000 {
1071 compatible = "fsl,imx6q-usdhc";
1072 reg = <0x0219c000 0x4000>;
1073 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
1074 clocks = <&clks IMX6QDL_CLK_USDHC4>,
1075 <&clks IMX6QDL_CLK_USDHC4>,
1076 <&clks IMX6QDL_CLK_USDHC4>;
1077 clock-names = "ipg", "ahb", "per";
1079 status = "disabled";
1083 #address-cells = <1>;
1085 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1086 reg = <0x021a0000 0x4000>;
1087 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
1088 clocks = <&clks IMX6QDL_CLK_I2C1>;
1089 status = "disabled";
1093 #address-cells = <1>;
1095 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1096 reg = <0x021a4000 0x4000>;
1097 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
1098 clocks = <&clks IMX6QDL_CLK_I2C2>;
1099 status = "disabled";
1103 #address-cells = <1>;
1105 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1106 reg = <0x021a8000 0x4000>;
1107 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
1108 clocks = <&clks IMX6QDL_CLK_I2C3>;
1109 status = "disabled";
1113 reg = <0x021ac000 0x4000>;
1116 mmdc0: mmdc@21b0000 { /* MMDC0 */
1117 compatible = "fsl,imx6q-mmdc";
1118 reg = <0x021b0000 0x4000>;
1121 mmdc1: mmdc@21b4000 { /* MMDC1 */
1122 reg = <0x021b4000 0x4000>;
1125 weim: weim@21b8000 {
1126 #address-cells = <2>;
1128 compatible = "fsl,imx6q-weim";
1129 reg = <0x021b8000 0x4000>;
1130 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1131 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
1132 fsl,weim-cs-gpr = <&gpr>;
1133 status = "disabled";
1136 ocotp: ocotp@21bc000 {
1137 compatible = "fsl,imx6q-ocotp", "syscon";
1138 reg = <0x021bc000 0x4000>;
1139 clocks = <&clks IMX6QDL_CLK_IIM>;
1142 tzasc@21d0000 { /* TZASC1 */
1143 reg = <0x021d0000 0x4000>;
1144 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1147 tzasc@21d4000 { /* TZASC2 */
1148 reg = <0x021d4000 0x4000>;
1149 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1152 audmux: audmux@21d8000 {
1153 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1154 reg = <0x021d8000 0x4000>;
1155 status = "disabled";
1158 mipi_csi: mipi@21dc000 {
1159 compatible = "fsl,imx6-mipi-csi2";
1160 reg = <0x021dc000 0x4000>;
1161 #address-cells = <1>;
1163 interrupts = <0 100 0x04>, <0 101 0x04>;
1164 clocks = <&clks IMX6QDL_CLK_HSI_TX>,
1165 <&clks IMX6QDL_CLK_VIDEO_27M>,
1166 <&clks IMX6QDL_CLK_EIM_PODF>;
1167 clock-names = "dphy", "ref", "pix";
1168 status = "disabled";
1171 mipi_dsi: mipi@21e0000 {
1172 reg = <0x021e0000 0x4000>;
1173 status = "disabled";
1176 #address-cells = <1>;
1182 mipi_mux_0: endpoint {
1183 remote-endpoint = <&ipu1_di0_mipi>;
1190 mipi_mux_1: endpoint {
1191 remote-endpoint = <&ipu1_di1_mipi>;
1198 compatible = "fsl,imx6q-vdoa";
1199 reg = <0x021e4000 0x4000>;
1200 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1201 clocks = <&clks IMX6QDL_CLK_VDOA>;
1204 uart2: serial@21e8000 {
1205 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1206 reg = <0x021e8000 0x4000>;
1207 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1208 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1209 <&clks IMX6QDL_CLK_UART_SERIAL>;
1210 clock-names = "ipg", "per";
1211 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1212 dma-names = "rx", "tx";
1213 status = "disabled";
1216 uart3: serial@21ec000 {
1217 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1218 reg = <0x021ec000 0x4000>;
1219 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1220 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1221 <&clks IMX6QDL_CLK_UART_SERIAL>;
1222 clock-names = "ipg", "per";
1223 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1224 dma-names = "rx", "tx";
1225 status = "disabled";
1228 uart4: serial@21f0000 {
1229 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1230 reg = <0x021f0000 0x4000>;
1231 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1232 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1233 <&clks IMX6QDL_CLK_UART_SERIAL>;
1234 clock-names = "ipg", "per";
1235 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1236 dma-names = "rx", "tx";
1237 status = "disabled";
1240 uart5: serial@21f4000 {
1241 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1242 reg = <0x021f4000 0x4000>;
1243 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1244 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1245 <&clks IMX6QDL_CLK_UART_SERIAL>;
1246 clock-names = "ipg", "per";
1247 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1248 dma-names = "rx", "tx";
1249 status = "disabled";
1254 #address-cells = <1>;
1256 compatible = "fsl,imx6q-ipu";
1257 reg = <0x02400000 0x400000>;
1258 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1259 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1260 clocks = <&clks IMX6QDL_CLK_IPU1>,
1261 <&clks IMX6QDL_CLK_IPU1_DI0>,
1262 <&clks IMX6QDL_CLK_IPU1_DI1>;
1263 clock-names = "bus", "di0", "di1";
1265 u-boot,dm-pre-reloc;
1270 ipu1_csi0_from_ipu1_csi0_mux: endpoint {
1271 remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
1280 #address-cells = <1>;
1284 ipu1_di0_disp0: endpoint@0 {
1288 ipu1_di0_hdmi: endpoint@1 {
1290 remote-endpoint = <&hdmi_mux_0>;
1293 ipu1_di0_mipi: endpoint@2 {
1295 remote-endpoint = <&mipi_mux_0>;
1298 ipu1_di0_lvds0: endpoint@3 {
1300 remote-endpoint = <&lvds0_mux_0>;
1303 ipu1_di0_lvds1: endpoint@4 {
1305 remote-endpoint = <&lvds1_mux_0>;
1310 #address-cells = <1>;
1314 ipu1_di1_disp1: endpoint@0 {
1318 ipu1_di1_hdmi: endpoint@1 {
1320 remote-endpoint = <&hdmi_mux_1>;
1323 ipu1_di1_mipi: endpoint@2 {
1325 remote-endpoint = <&mipi_mux_1>;
1328 ipu1_di1_lvds0: endpoint@3 {
1330 remote-endpoint = <&lvds0_mux_1>;
1333 ipu1_di1_lvds1: endpoint@4 {
1335 remote-endpoint = <&lvds1_mux_1>;