1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright 2011 Freescale Semiconductor, Inc.
4 // Copyright 2011 Linaro Ltd.
6 #include <dt-bindings/clock/imx6qdl-clock.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 * The decompressor and also some bootloaders rely on a
14 * pre-existing /chosen node to be available to insert the
15 * command line and merge other ATAGS info.
16 * Also for U-Boot there must be a pre-existing /memory node.
19 memory { device_type = "memory"; };
56 compatible = "fsl,imx-ckil", "fixed-clock";
58 clock-frequency = <32768>;
62 compatible = "fsl,imx-ckih1", "fixed-clock";
64 clock-frequency = <0>;
68 compatible = "fsl,imx-osc", "fixed-clock";
70 clock-frequency = <24000000>;
75 compatible = "fsl,imx6q-tempmon";
76 interrupt-parent = <&gpc>;
77 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
78 fsl,tempmon = <&anatop>;
79 fsl,tempmon-data = <&ocotp>;
80 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
86 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
99 lvds0_mux_0: endpoint {
100 remote-endpoint = <&ipu1_di0_lvds0>;
107 lvds0_mux_1: endpoint {
108 remote-endpoint = <&ipu1_di1_lvds0>;
114 #address-cells = <1>;
122 lvds1_mux_0: endpoint {
123 remote-endpoint = <&ipu1_di0_lvds1>;
130 lvds1_mux_1: endpoint {
131 remote-endpoint = <&ipu1_di1_lvds1>;
138 compatible = "arm,cortex-a9-pmu";
139 interrupt-parent = <&gpc>;
140 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
144 #address-cells = <1>;
146 compatible = "simple-bus";
147 interrupt-parent = <&gpc>;
151 dma_apbh: dma-apbh@110000 {
152 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
153 reg = <0x00110000 0x2000>;
154 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
155 <0 13 IRQ_TYPE_LEVEL_HIGH>,
156 <0 13 IRQ_TYPE_LEVEL_HIGH>,
157 <0 13 IRQ_TYPE_LEVEL_HIGH>;
158 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
161 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
164 gpmi: gpmi-nand@112000 {
165 compatible = "fsl,imx6q-gpmi-nand";
166 #address-cells = <1>;
168 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
169 reg-names = "gpmi-nand", "bch";
170 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
171 interrupt-names = "bch";
172 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
173 <&clks IMX6QDL_CLK_GPMI_APB>,
174 <&clks IMX6QDL_CLK_GPMI_BCH>,
175 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
176 <&clks IMX6QDL_CLK_PER1_BCH>;
177 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
178 "gpmi_bch_apb", "per1_bch";
179 dmas = <&dma_apbh 0>;
185 #address-cells = <1>;
187 reg = <0x00120000 0x9000>;
188 interrupts = <0 115 0x04>;
190 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
191 <&clks IMX6QDL_CLK_HDMI_ISFR>;
192 clock-names = "iahb", "isfr";
198 hdmi_mux_0: endpoint {
199 remote-endpoint = <&ipu1_di0_hdmi>;
206 hdmi_mux_1: endpoint {
207 remote-endpoint = <&ipu1_di1_hdmi>;
213 compatible = "vivante,gc";
214 reg = <0x00130000 0x4000>;
215 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
217 <&clks IMX6QDL_CLK_GPU3D_CORE>,
218 <&clks IMX6QDL_CLK_GPU3D_SHADER>;
219 clock-names = "bus", "core", "shader";
220 power-domains = <&pd_pu>;
224 compatible = "vivante,gc";
225 reg = <0x00134000 0x4000>;
226 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
228 <&clks IMX6QDL_CLK_GPU2D_CORE>;
229 clock-names = "bus", "core";
230 power-domains = <&pd_pu>;
234 compatible = "arm,cortex-a9-twd-timer";
235 reg = <0x00a00600 0x20>;
236 interrupts = <1 13 0xf01>;
237 interrupt-parent = <&intc>;
238 clocks = <&clks IMX6QDL_CLK_TWD>;
241 intc: interrupt-controller@a01000 {
242 compatible = "arm,cortex-a9-gic";
243 #interrupt-cells = <3>;
244 interrupt-controller;
245 reg = <0x00a01000 0x1000>,
247 interrupt-parent = <&intc>;
250 L2: l2-cache@a02000 {
251 compatible = "arm,pl310-cache";
252 reg = <0x00a02000 0x1000>;
253 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
256 arm,tag-latency = <4 2 3>;
257 arm,data-latency = <4 2 3>;
262 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
263 reg = <0x01ffc000 0x04000>,
264 <0x01f00000 0x80000>;
265 reg-names = "dbi", "config";
266 #address-cells = <3>;
269 bus-range = <0x00 0xff>;
270 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
271 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
273 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
274 interrupt-names = "msi";
275 #interrupt-cells = <1>;
276 interrupt-map-mask = <0 0 0 0x7>;
277 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
278 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
279 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
280 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
282 <&clks IMX6QDL_CLK_LVDS1_GATE>,
283 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
284 clock-names = "pcie", "pcie_bus", "pcie_phy";
288 aips-bus@2000000 { /* AIPS1 */
289 compatible = "fsl,aips-bus", "simple-bus";
290 #address-cells = <1>;
292 reg = <0x02000000 0x100000>;
296 compatible = "fsl,spba-bus", "simple-bus";
297 #address-cells = <1>;
299 reg = <0x02000000 0x40000>;
302 spdif: spdif@2004000 {
303 compatible = "fsl,imx35-spdif";
304 reg = <0x02004000 0x4000>;
305 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
306 dmas = <&sdma 14 18 0>,
308 dma-names = "rx", "tx";
309 clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
310 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
311 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
312 <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
313 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
314 clock-names = "core", "rxtx0",
322 ecspi1: spi@2008000 {
323 #address-cells = <1>;
325 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
326 reg = <0x02008000 0x4000>;
327 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&clks IMX6QDL_CLK_ECSPI1>,
329 <&clks IMX6QDL_CLK_ECSPI1>;
330 clock-names = "ipg", "per";
331 dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
332 dma-names = "rx", "tx";
336 ecspi2: spi@200c000 {
337 #address-cells = <1>;
339 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
340 reg = <0x0200c000 0x4000>;
341 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&clks IMX6QDL_CLK_ECSPI2>,
343 <&clks IMX6QDL_CLK_ECSPI2>;
344 clock-names = "ipg", "per";
345 dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
346 dma-names = "rx", "tx";
350 ecspi3: spi@2010000 {
351 #address-cells = <1>;
353 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
354 reg = <0x02010000 0x4000>;
355 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&clks IMX6QDL_CLK_ECSPI3>,
357 <&clks IMX6QDL_CLK_ECSPI3>;
358 clock-names = "ipg", "per";
359 dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
360 dma-names = "rx", "tx";
364 ecspi4: spi@2014000 {
365 #address-cells = <1>;
367 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
368 reg = <0x02014000 0x4000>;
369 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&clks IMX6QDL_CLK_ECSPI4>,
371 <&clks IMX6QDL_CLK_ECSPI4>;
372 clock-names = "ipg", "per";
373 dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
374 dma-names = "rx", "tx";
378 uart1: serial@2020000 {
379 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
380 reg = <0x02020000 0x4000>;
381 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
382 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
383 <&clks IMX6QDL_CLK_UART_SERIAL>;
384 clock-names = "ipg", "per";
385 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
386 dma-names = "rx", "tx";
391 #sound-dai-cells = <0>;
392 compatible = "fsl,imx35-esai";
393 reg = <0x02024000 0x4000>;
394 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
396 <&clks IMX6QDL_CLK_ESAI_MEM>,
397 <&clks IMX6QDL_CLK_ESAI_EXTAL>,
398 <&clks IMX6QDL_CLK_ESAI_IPG>,
399 <&clks IMX6QDL_CLK_SPBA>;
400 clock-names = "core", "mem", "extal", "fsys", "spba";
401 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
402 dma-names = "rx", "tx";
407 #sound-dai-cells = <0>;
408 compatible = "fsl,imx6q-ssi",
410 reg = <0x02028000 0x4000>;
411 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
412 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
413 <&clks IMX6QDL_CLK_SSI1>;
414 clock-names = "ipg", "baud";
415 dmas = <&sdma 37 1 0>,
417 dma-names = "rx", "tx";
418 fsl,fifo-depth = <15>;
423 #sound-dai-cells = <0>;
424 compatible = "fsl,imx6q-ssi",
426 reg = <0x0202c000 0x4000>;
427 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
429 <&clks IMX6QDL_CLK_SSI2>;
430 clock-names = "ipg", "baud";
431 dmas = <&sdma 41 1 0>,
433 dma-names = "rx", "tx";
434 fsl,fifo-depth = <15>;
439 #sound-dai-cells = <0>;
440 compatible = "fsl,imx6q-ssi",
442 reg = <0x02030000 0x4000>;
443 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
445 <&clks IMX6QDL_CLK_SSI3>;
446 clock-names = "ipg", "baud";
447 dmas = <&sdma 45 1 0>,
449 dma-names = "rx", "tx";
450 fsl,fifo-depth = <15>;
455 compatible = "fsl,imx53-asrc";
456 reg = <0x02034000 0x4000>;
457 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
459 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
460 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
461 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
462 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
463 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
464 <&clks IMX6QDL_CLK_SPBA>;
465 clock-names = "mem", "ipg", "asrck_0",
466 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
467 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
468 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
469 "asrck_d", "asrck_e", "asrck_f", "spba";
470 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
471 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
472 dma-names = "rxa", "rxb", "rxc",
474 fsl,asrc-rate = <48000>;
475 fsl,asrc-width = <16>;
480 reg = <0x0203c000 0x4000>;
485 compatible = "cnm,coda960";
486 reg = <0x02040000 0x3c000>;
487 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
488 <0 3 IRQ_TYPE_LEVEL_HIGH>;
489 interrupt-names = "bit", "jpeg";
490 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
491 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
492 clock-names = "per", "ahb";
493 power-domains = <&pd_pu>;
498 aipstz@207c000 { /* AIPSTZ1 */
499 reg = <0x0207c000 0x4000>;
504 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
505 reg = <0x02080000 0x4000>;
506 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
507 clocks = <&clks IMX6QDL_CLK_IPG>,
508 <&clks IMX6QDL_CLK_PWM1>;
509 clock-names = "ipg", "per";
515 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
516 reg = <0x02084000 0x4000>;
517 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&clks IMX6QDL_CLK_IPG>,
519 <&clks IMX6QDL_CLK_PWM2>;
520 clock-names = "ipg", "per";
526 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
527 reg = <0x02088000 0x4000>;
528 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
529 clocks = <&clks IMX6QDL_CLK_IPG>,
530 <&clks IMX6QDL_CLK_PWM3>;
531 clock-names = "ipg", "per";
537 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
538 reg = <0x0208c000 0x4000>;
539 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&clks IMX6QDL_CLK_IPG>,
541 <&clks IMX6QDL_CLK_PWM4>;
542 clock-names = "ipg", "per";
546 can1: flexcan@2090000 {
547 compatible = "fsl,imx6q-flexcan";
548 reg = <0x02090000 0x4000>;
549 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
550 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
551 <&clks IMX6QDL_CLK_CAN1_SERIAL>;
552 clock-names = "ipg", "per";
556 can2: flexcan@2094000 {
557 compatible = "fsl,imx6q-flexcan";
558 reg = <0x02094000 0x4000>;
559 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
560 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
561 <&clks IMX6QDL_CLK_CAN2_SERIAL>;
562 clock-names = "ipg", "per";
567 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
568 reg = <0x02098000 0x4000>;
569 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
571 <&clks IMX6QDL_CLK_GPT_IPG_PER>,
572 <&clks IMX6QDL_CLK_GPT_3M>;
573 clock-names = "ipg", "per", "osc_per";
576 gpio1: gpio@209c000 {
577 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
578 reg = <0x0209c000 0x4000>;
579 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
580 <0 67 IRQ_TYPE_LEVEL_HIGH>;
583 interrupt-controller;
584 #interrupt-cells = <2>;
587 gpio2: gpio@20a0000 {
588 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
589 reg = <0x020a0000 0x4000>;
590 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
591 <0 69 IRQ_TYPE_LEVEL_HIGH>;
594 interrupt-controller;
595 #interrupt-cells = <2>;
598 gpio3: gpio@20a4000 {
599 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
600 reg = <0x020a4000 0x4000>;
601 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
602 <0 71 IRQ_TYPE_LEVEL_HIGH>;
605 interrupt-controller;
606 #interrupt-cells = <2>;
609 gpio4: gpio@20a8000 {
610 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
611 reg = <0x020a8000 0x4000>;
612 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
613 <0 73 IRQ_TYPE_LEVEL_HIGH>;
616 interrupt-controller;
617 #interrupt-cells = <2>;
620 gpio5: gpio@20ac000 {
621 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
622 reg = <0x020ac000 0x4000>;
623 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
624 <0 75 IRQ_TYPE_LEVEL_HIGH>;
627 interrupt-controller;
628 #interrupt-cells = <2>;
631 gpio6: gpio@20b0000 {
632 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
633 reg = <0x020b0000 0x4000>;
634 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
635 <0 77 IRQ_TYPE_LEVEL_HIGH>;
638 interrupt-controller;
639 #interrupt-cells = <2>;
642 gpio7: gpio@20b4000 {
643 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
644 reg = <0x020b4000 0x4000>;
645 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
646 <0 79 IRQ_TYPE_LEVEL_HIGH>;
649 interrupt-controller;
650 #interrupt-cells = <2>;
654 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
655 reg = <0x020b8000 0x4000>;
656 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
657 clocks = <&clks IMX6QDL_CLK_IPG>;
661 wdog1: wdog@20bc000 {
662 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
663 reg = <0x020bc000 0x4000>;
664 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
665 clocks = <&clks IMX6QDL_CLK_DUMMY>;
668 wdog2: wdog@20c0000 {
669 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
670 reg = <0x020c0000 0x4000>;
671 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
672 clocks = <&clks IMX6QDL_CLK_DUMMY>;
677 compatible = "fsl,imx6q-ccm";
678 reg = <0x020c4000 0x4000>;
679 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
680 <0 88 IRQ_TYPE_LEVEL_HIGH>;
684 anatop: anatop@20c8000 {
685 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
686 reg = <0x020c8000 0x1000>;
687 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
688 <0 54 IRQ_TYPE_LEVEL_HIGH>,
689 <0 127 IRQ_TYPE_LEVEL_HIGH>;
692 compatible = "fsl,anatop-regulator";
693 regulator-name = "vdd1p1";
694 regulator-min-microvolt = <1000000>;
695 regulator-max-microvolt = <1200000>;
697 anatop-reg-offset = <0x110>;
698 anatop-vol-bit-shift = <8>;
699 anatop-vol-bit-width = <5>;
700 anatop-min-bit-val = <4>;
701 anatop-min-voltage = <800000>;
702 anatop-max-voltage = <1375000>;
703 anatop-enable-bit = <0>;
707 compatible = "fsl,anatop-regulator";
708 regulator-name = "vdd3p0";
709 regulator-min-microvolt = <2800000>;
710 regulator-max-microvolt = <3150000>;
712 anatop-reg-offset = <0x120>;
713 anatop-vol-bit-shift = <8>;
714 anatop-vol-bit-width = <5>;
715 anatop-min-bit-val = <0>;
716 anatop-min-voltage = <2625000>;
717 anatop-max-voltage = <3400000>;
718 anatop-enable-bit = <0>;
722 compatible = "fsl,anatop-regulator";
723 regulator-name = "vdd2p5";
724 regulator-min-microvolt = <2250000>;
725 regulator-max-microvolt = <2750000>;
727 anatop-reg-offset = <0x130>;
728 anatop-vol-bit-shift = <8>;
729 anatop-vol-bit-width = <5>;
730 anatop-min-bit-val = <0>;
731 anatop-min-voltage = <2100000>;
732 anatop-max-voltage = <2875000>;
733 anatop-enable-bit = <0>;
736 reg_arm: regulator-vddcore {
737 compatible = "fsl,anatop-regulator";
738 regulator-name = "vddarm";
739 regulator-min-microvolt = <725000>;
740 regulator-max-microvolt = <1450000>;
742 anatop-reg-offset = <0x140>;
743 anatop-vol-bit-shift = <0>;
744 anatop-vol-bit-width = <5>;
745 anatop-delay-reg-offset = <0x170>;
746 anatop-delay-bit-shift = <24>;
747 anatop-delay-bit-width = <2>;
748 anatop-min-bit-val = <1>;
749 anatop-min-voltage = <725000>;
750 anatop-max-voltage = <1450000>;
753 reg_pu: regulator-vddpu {
754 compatible = "fsl,anatop-regulator";
755 regulator-name = "vddpu";
756 regulator-min-microvolt = <725000>;
757 regulator-max-microvolt = <1450000>;
758 regulator-enable-ramp-delay = <150>;
759 anatop-reg-offset = <0x140>;
760 anatop-vol-bit-shift = <9>;
761 anatop-vol-bit-width = <5>;
762 anatop-delay-reg-offset = <0x170>;
763 anatop-delay-bit-shift = <26>;
764 anatop-delay-bit-width = <2>;
765 anatop-min-bit-val = <1>;
766 anatop-min-voltage = <725000>;
767 anatop-max-voltage = <1450000>;
770 reg_soc: regulator-vddsoc {
771 compatible = "fsl,anatop-regulator";
772 regulator-name = "vddsoc";
773 regulator-min-microvolt = <725000>;
774 regulator-max-microvolt = <1450000>;
776 anatop-reg-offset = <0x140>;
777 anatop-vol-bit-shift = <18>;
778 anatop-vol-bit-width = <5>;
779 anatop-delay-reg-offset = <0x170>;
780 anatop-delay-bit-shift = <28>;
781 anatop-delay-bit-width = <2>;
782 anatop-min-bit-val = <1>;
783 anatop-min-voltage = <725000>;
784 anatop-max-voltage = <1450000>;
788 usbphy1: usbphy@20c9000 {
789 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
790 reg = <0x020c9000 0x1000>;
791 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
792 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
793 fsl,anatop = <&anatop>;
796 usbphy2: usbphy@20ca000 {
797 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
798 reg = <0x020ca000 0x1000>;
799 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
800 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
801 fsl,anatop = <&anatop>;
805 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
806 reg = <0x020cc000 0x4000>;
808 snvs_rtc: snvs-rtc-lp {
809 compatible = "fsl,sec-v4.0-mon-rtc-lp";
812 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
813 <0 20 IRQ_TYPE_LEVEL_HIGH>;
816 snvs_poweroff: snvs-poweroff {
817 compatible = "syscon-poweroff";
825 snvs_lpgpr: snvs-lpgpr {
826 compatible = "fsl,imx6q-snvs-lpgpr";
830 epit1: epit@20d0000 { /* EPIT1 */
831 reg = <0x020d0000 0x4000>;
832 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
835 epit2: epit@20d4000 { /* EPIT2 */
836 reg = <0x020d4000 0x4000>;
837 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
841 compatible = "fsl,imx6q-src", "fsl,imx51-src";
842 reg = <0x020d8000 0x4000>;
843 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
844 <0 96 IRQ_TYPE_LEVEL_HIGH>;
849 compatible = "fsl,imx6q-gpc";
850 reg = <0x020dc000 0x4000>;
851 interrupt-controller;
852 #interrupt-cells = <3>;
853 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
854 <0 90 IRQ_TYPE_LEVEL_HIGH>;
855 interrupt-parent = <&intc>;
856 clocks = <&clks IMX6QDL_CLK_IPG>;
860 #address-cells = <1>;
865 #power-domain-cells = <0>;
867 pd_pu: power-domain@1 {
869 #power-domain-cells = <0>;
870 power-supply = <®_pu>;
871 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
872 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
873 <&clks IMX6QDL_CLK_GPU2D_CORE>,
874 <&clks IMX6QDL_CLK_GPU2D_AXI>,
875 <&clks IMX6QDL_CLK_OPENVG_AXI>,
876 <&clks IMX6QDL_CLK_VPU_AXI>;
881 gpr: iomuxc-gpr@20e0000 {
882 compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
883 reg = <0x20e0000 0x38>;
885 mux: mux-controller {
886 compatible = "mmio-mux";
887 #mux-control-cells = <1>;
891 iomuxc: iomuxc@20e0000 {
892 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
893 reg = <0x20e0000 0x4000>;
896 dcic1: dcic@20e4000 {
897 reg = <0x020e4000 0x4000>;
898 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
901 dcic2: dcic@20e8000 {
902 reg = <0x020e8000 0x4000>;
903 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
907 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
908 reg = <0x020ec000 0x4000>;
909 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
910 clocks = <&clks IMX6QDL_CLK_SDMA>,
911 <&clks IMX6QDL_CLK_SDMA>;
912 clock-names = "ipg", "ahb";
914 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
918 aips-bus@2100000 { /* AIPS2 */
919 compatible = "fsl,aips-bus", "simple-bus";
920 #address-cells = <1>;
922 reg = <0x02100000 0x100000>;
925 crypto: caam@2100000 {
926 compatible = "fsl,sec-v4.0";
927 #address-cells = <1>;
929 reg = <0x2100000 0x10000>;
930 ranges = <0 0x2100000 0x10000>;
931 clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
932 <&clks IMX6QDL_CLK_CAAM_ACLK>,
933 <&clks IMX6QDL_CLK_CAAM_IPG>,
934 <&clks IMX6QDL_CLK_EIM_SLOW>;
935 clock-names = "mem", "aclk", "ipg", "emi_slow";
938 compatible = "fsl,sec-v4.0-job-ring";
939 reg = <0x1000 0x1000>;
940 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
944 compatible = "fsl,sec-v4.0-job-ring";
945 reg = <0x2000 0x1000>;
946 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
950 aipstz@217c000 { /* AIPSTZ2 */
951 reg = <0x0217c000 0x4000>;
954 usbotg: usb@2184000 {
955 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
956 reg = <0x02184000 0x200>;
957 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
958 clocks = <&clks IMX6QDL_CLK_USBOH3>;
959 fsl,usbphy = <&usbphy1>;
960 fsl,usbmisc = <&usbmisc 0>;
961 ahb-burst-config = <0x0>;
962 tx-burst-size-dword = <0x10>;
963 rx-burst-size-dword = <0x10>;
968 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
969 reg = <0x02184200 0x200>;
970 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
971 clocks = <&clks IMX6QDL_CLK_USBOH3>;
972 fsl,usbphy = <&usbphy2>;
973 fsl,usbmisc = <&usbmisc 1>;
975 ahb-burst-config = <0x0>;
976 tx-burst-size-dword = <0x10>;
977 rx-burst-size-dword = <0x10>;
982 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
983 reg = <0x02184400 0x200>;
984 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
985 clocks = <&clks IMX6QDL_CLK_USBOH3>;
986 fsl,usbmisc = <&usbmisc 2>;
988 ahb-burst-config = <0x0>;
989 tx-burst-size-dword = <0x10>;
990 rx-burst-size-dword = <0x10>;
995 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
996 reg = <0x02184600 0x200>;
997 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
998 clocks = <&clks IMX6QDL_CLK_USBOH3>;
999 fsl,usbmisc = <&usbmisc 3>;
1001 ahb-burst-config = <0x0>;
1002 tx-burst-size-dword = <0x10>;
1003 rx-burst-size-dword = <0x10>;
1004 status = "disabled";
1007 usbmisc: usbmisc@2184800 {
1009 compatible = "fsl,imx6q-usbmisc";
1010 reg = <0x02184800 0x200>;
1011 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1014 fec: ethernet@2188000 {
1015 compatible = "fsl,imx6q-fec";
1016 reg = <0x02188000 0x4000>;
1017 interrupt-names = "int0", "pps";
1018 interrupts-extended =
1019 <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
1020 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
1021 clocks = <&clks IMX6QDL_CLK_ENET>,
1022 <&clks IMX6QDL_CLK_ENET>,
1023 <&clks IMX6QDL_CLK_ENET_REF>;
1024 clock-names = "ipg", "ahb", "ptp";
1025 status = "disabled";
1029 reg = <0x0218c000 0x4000>;
1030 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
1031 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1032 <0 126 IRQ_TYPE_LEVEL_HIGH>;
1035 usdhc1: usdhc@2190000 {
1036 compatible = "fsl,imx6q-usdhc";
1037 reg = <0x02190000 0x4000>;
1038 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
1039 clocks = <&clks IMX6QDL_CLK_USDHC1>,
1040 <&clks IMX6QDL_CLK_USDHC1>,
1041 <&clks IMX6QDL_CLK_USDHC1>;
1042 clock-names = "ipg", "ahb", "per";
1044 status = "disabled";
1047 usdhc2: usdhc@2194000 {
1048 compatible = "fsl,imx6q-usdhc";
1049 reg = <0x02194000 0x4000>;
1050 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
1051 clocks = <&clks IMX6QDL_CLK_USDHC2>,
1052 <&clks IMX6QDL_CLK_USDHC2>,
1053 <&clks IMX6QDL_CLK_USDHC2>;
1054 clock-names = "ipg", "ahb", "per";
1056 status = "disabled";
1059 usdhc3: usdhc@2198000 {
1060 compatible = "fsl,imx6q-usdhc";
1061 reg = <0x02198000 0x4000>;
1062 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
1063 clocks = <&clks IMX6QDL_CLK_USDHC3>,
1064 <&clks IMX6QDL_CLK_USDHC3>,
1065 <&clks IMX6QDL_CLK_USDHC3>;
1066 clock-names = "ipg", "ahb", "per";
1068 status = "disabled";
1071 usdhc4: usdhc@219c000 {
1072 compatible = "fsl,imx6q-usdhc";
1073 reg = <0x0219c000 0x4000>;
1074 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
1075 clocks = <&clks IMX6QDL_CLK_USDHC4>,
1076 <&clks IMX6QDL_CLK_USDHC4>,
1077 <&clks IMX6QDL_CLK_USDHC4>;
1078 clock-names = "ipg", "ahb", "per";
1080 status = "disabled";
1084 #address-cells = <1>;
1086 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1087 reg = <0x021a0000 0x4000>;
1088 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
1089 clocks = <&clks IMX6QDL_CLK_I2C1>;
1090 status = "disabled";
1094 #address-cells = <1>;
1096 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1097 reg = <0x021a4000 0x4000>;
1098 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
1099 clocks = <&clks IMX6QDL_CLK_I2C2>;
1100 status = "disabled";
1104 #address-cells = <1>;
1106 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1107 reg = <0x021a8000 0x4000>;
1108 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
1109 clocks = <&clks IMX6QDL_CLK_I2C3>;
1110 status = "disabled";
1114 reg = <0x021ac000 0x4000>;
1117 mmdc0: mmdc@21b0000 { /* MMDC0 */
1118 compatible = "fsl,imx6q-mmdc";
1119 reg = <0x021b0000 0x4000>;
1122 mmdc1: mmdc@21b4000 { /* MMDC1 */
1123 reg = <0x021b4000 0x4000>;
1126 weim: weim@21b8000 {
1127 #address-cells = <2>;
1129 compatible = "fsl,imx6q-weim";
1130 reg = <0x021b8000 0x4000>;
1131 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1132 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
1133 fsl,weim-cs-gpr = <&gpr>;
1134 status = "disabled";
1137 ocotp: ocotp@21bc000 {
1138 compatible = "fsl,imx6q-ocotp", "syscon";
1139 reg = <0x021bc000 0x4000>;
1140 clocks = <&clks IMX6QDL_CLK_IIM>;
1143 tzasc@21d0000 { /* TZASC1 */
1144 reg = <0x021d0000 0x4000>;
1145 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1148 tzasc@21d4000 { /* TZASC2 */
1149 reg = <0x021d4000 0x4000>;
1150 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1153 audmux: audmux@21d8000 {
1154 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1155 reg = <0x021d8000 0x4000>;
1156 status = "disabled";
1159 mipi_csi: mipi@21dc000 {
1160 compatible = "fsl,imx6-mipi-csi2";
1161 reg = <0x021dc000 0x4000>;
1162 #address-cells = <1>;
1164 interrupts = <0 100 0x04>, <0 101 0x04>;
1165 clocks = <&clks IMX6QDL_CLK_HSI_TX>,
1166 <&clks IMX6QDL_CLK_VIDEO_27M>,
1167 <&clks IMX6QDL_CLK_EIM_PODF>;
1168 clock-names = "dphy", "ref", "pix";
1169 status = "disabled";
1172 mipi_dsi: mipi@21e0000 {
1173 reg = <0x021e0000 0x4000>;
1174 status = "disabled";
1177 #address-cells = <1>;
1183 mipi_mux_0: endpoint {
1184 remote-endpoint = <&ipu1_di0_mipi>;
1191 mipi_mux_1: endpoint {
1192 remote-endpoint = <&ipu1_di1_mipi>;
1199 compatible = "fsl,imx6q-vdoa";
1200 reg = <0x021e4000 0x4000>;
1201 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1202 clocks = <&clks IMX6QDL_CLK_VDOA>;
1205 uart2: serial@21e8000 {
1206 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1207 reg = <0x021e8000 0x4000>;
1208 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1209 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1210 <&clks IMX6QDL_CLK_UART_SERIAL>;
1211 clock-names = "ipg", "per";
1212 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1213 dma-names = "rx", "tx";
1214 status = "disabled";
1217 uart3: serial@21ec000 {
1218 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1219 reg = <0x021ec000 0x4000>;
1220 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1221 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1222 <&clks IMX6QDL_CLK_UART_SERIAL>;
1223 clock-names = "ipg", "per";
1224 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1225 dma-names = "rx", "tx";
1226 status = "disabled";
1229 uart4: serial@21f0000 {
1230 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1231 reg = <0x021f0000 0x4000>;
1232 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1233 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1234 <&clks IMX6QDL_CLK_UART_SERIAL>;
1235 clock-names = "ipg", "per";
1236 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1237 dma-names = "rx", "tx";
1238 status = "disabled";
1241 uart5: serial@21f4000 {
1242 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1243 reg = <0x021f4000 0x4000>;
1244 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1245 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1246 <&clks IMX6QDL_CLK_UART_SERIAL>;
1247 clock-names = "ipg", "per";
1248 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1249 dma-names = "rx", "tx";
1250 status = "disabled";
1255 #address-cells = <1>;
1257 compatible = "fsl,imx6q-ipu";
1258 reg = <0x02400000 0x400000>;
1259 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1260 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1261 clocks = <&clks IMX6QDL_CLK_IPU1>,
1262 <&clks IMX6QDL_CLK_IPU1_DI0>,
1263 <&clks IMX6QDL_CLK_IPU1_DI1>;
1264 clock-names = "bus", "di0", "di1";
1266 u-boot,dm-pre-reloc;
1271 ipu1_csi0_from_ipu1_csi0_mux: endpoint {
1272 remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
1281 #address-cells = <1>;
1285 ipu1_di0_disp0: endpoint@0 {
1289 ipu1_di0_hdmi: endpoint@1 {
1291 remote-endpoint = <&hdmi_mux_0>;
1294 ipu1_di0_mipi: endpoint@2 {
1296 remote-endpoint = <&mipi_mux_0>;
1299 ipu1_di0_lvds0: endpoint@3 {
1301 remote-endpoint = <&lvds0_mux_0>;
1304 ipu1_di0_lvds1: endpoint@4 {
1306 remote-endpoint = <&lvds1_mux_0>;
1311 #address-cells = <1>;
1315 ipu1_di1_disp1: endpoint@0 {
1319 ipu1_di1_hdmi: endpoint@1 {
1321 remote-endpoint = <&hdmi_mux_1>;
1324 ipu1_di1_mipi: endpoint@2 {
1326 remote-endpoint = <&mipi_mux_1>;
1329 ipu1_di1_lvds0: endpoint@3 {
1331 remote-endpoint = <&lvds0_mux_1>;
1334 ipu1_di1_lvds1: endpoint@4 {
1336 remote-endpoint = <&lvds1_mux_1>;