1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright 2018 Technexion Ltd.
5 // Author: Wig Cheng <wig.cheng@technexion.com>
6 // Richard Hu <richard.hu@technexion.com>
7 // Tapani Utriainen <tapani@technexion.com>
9 #include <dt-bindings/gpio/gpio.h>
21 reg_2p5v: regulator-2p5v {
22 compatible = "regulator-fixed";
23 regulator-name = "2P5V";
24 regulator-min-microvolt = <2500000>;
25 regulator-max-microvolt = <2500000>;
29 reg_3p3v: regulator-3p3v {
30 compatible = "regulator-fixed";
31 regulator-name = "3P3V";
32 regulator-min-microvolt = <3300000>;
33 regulator-max-microvolt = <3300000>;
37 reg_1p8v: regulator-1p8v {
38 compatible = "regulator-fixed";
39 regulator-name = "1P8V";
40 regulator-min-microvolt = <1800000>;
41 regulator-max-microvolt = <1800000>;
45 reg_usb_otg_vbus: regulator-usb-otg-vbus {
46 pinctrl-names = "default";
47 pinctrl-0 = <&pinctrl_usbotg_vbus>;
48 compatible = "regulator-fixed";
49 regulator-name = "usb_otg_vbus";
50 regulator-min-microvolt = <5000000>;
51 regulator-max-microvolt = <5000000>;
52 gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_audmux>;
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_flexcan1>;
69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_flexcan2>;
75 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
76 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
77 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
78 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_ecspi2>;
84 cs-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>;
89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_enet>;
91 phy-mode = "rgmii-id";
92 phy-reset-gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;
97 ddc-i2c-bus = <&i2c2>;
102 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_i2c1>;
108 clock-frequency = <100000>;
109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_i2c2>;
115 pinctrl-names = "default";
116 pinctrl-0 = <&pinctrl_i2c3>;
121 pinctrl-names = "default";
122 pinctrl-0 = <&pinctrl_pcie_reset>;
123 reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>;
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_pwm1>;
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_pwm2>;
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_pwm3>;
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_pwm4>;
156 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_uart1>;
161 &uart2 { /* Bluetooth module */
162 pinctrl-names = "default";
163 pinctrl-0 = <&pinctrl_uart2>;
169 pinctrl-names = "default";
170 pinctrl-0 = <&pinctrl_uart3>;
180 vbus-supply = <®_usb_otg_vbus>;
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_usbotg>;
183 disable-over-current;
189 pinctrl-names = "default";
190 pinctrl-0 = <&pinctrl_usdhc1>;
192 cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
196 &usdhc2 { /* Wifi/BT */
197 pinctrl-names = "default";
198 pinctrl-0 = <&pinctrl_usdhc2>;
201 keep-power-in-suspend;
207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_usdhc3>;
216 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_hog>;
219 pinctrl_hog: hoggrp {
221 MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x4001b0b5 /* PICO_P24 */
222 MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x4001b0b5 /* PICO_P25 */
223 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x4001b0b5 /* PICO_P26 */
224 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b5 /* PICO_P28 */
225 MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b0b5 /* PICO_P30 */
226 MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b0b5 /* PICO_P32 */
227 MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x4001b0b5 /* PICO_P34 */
228 MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x4001b0b5 /* PICO_P42 */
229 MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x4001b0b5 /* PICO_P44 */
230 MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x4001b0b5 /* PICO_P48 */
234 pinctrl_audmux: audmuxgrp {
236 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
237 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
238 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
239 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
243 pinctrl_ecspi1: ecspi1grp {
245 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
246 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
247 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
248 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x000f0b0
252 pinctrl_ecspi2: ecspi2grp {
254 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x1b0b1
255 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x1b0b1
256 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x1b0b1
257 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000f0b0
258 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x000f0b0
262 pinctrl_enet: enetgrp {
264 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
265 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
266 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
267 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
268 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
269 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
270 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
271 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
272 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
273 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
274 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
275 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
276 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
277 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
278 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
279 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
280 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1f0b1
284 pinctrl_flexcan1: flexcan1grp {
286 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
287 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
291 pinctrl_flexcan2: flexcan2grp {
293 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
294 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
298 pinctrl_i2c1: i2c1grp {
300 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
301 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
305 pinctrl_i2c2: i2c2grp {
307 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
308 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
312 pinctrl_i2c3: i2c3grp {
314 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
315 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
319 pinctrl_pcie_reset: pciegrp {
321 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x130b0
325 pinctrl_pwm1: pwm1grp {
327 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
331 pinctrl_pwm2: pwm2grp {
333 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
337 pinctrl_pwm3: pwm3grp {
339 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
343 pinctrl_pwm4: pwm4grp {
345 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
349 pinctrl_uart1: uart1grp {
351 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
352 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
356 pinctrl_uart2: uart2grp {
358 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
359 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
360 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
361 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
365 pinctrl_uart3: uart3grp {
367 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
368 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
369 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
370 MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
374 pinctrl_usbotg: usbotggrp {
376 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
380 pinctrl_usbotg_vbus: usbotgvbusgrp {
382 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
386 pinctrl_usdhc1: usdhc1grp {
388 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
389 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x17071
390 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
391 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
392 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
393 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
394 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
398 pinctrl_usdhc2: usdhc2grp {
400 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
401 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
402 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
403 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
404 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
405 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
409 pinctrl_usdhc3: usdhc3grp {
411 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
412 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
413 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
414 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
415 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
416 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
417 MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0xb0b1
418 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
419 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
420 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
421 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059