arch/arm/dts/imx6qdl-icore.dtsi

   1 /*
   2  * Copyright (C) 2016 Amarula Solutions B.V.
   3  * Copyright (C) 2016 Engicam S.r.l.
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License
  12  *     version 2 as published by the Free Software Foundation.
  13  *
  14  *     This file is distributed in the hope that it will be useful
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/gpio/gpio.h>
  44 #include <dt-bindings/input/input.h>
  45
  46 / {
  47         aliases {
  48                 mmc1 = &usdhc3;
  49         };
  50
  51         memory {
  52                 reg = <0x10000000 0x80000000>;
  53         };
  54
  55         reg_3p3v: regulator-3p3v {
  56                 compatible = "regulator-fixed";
  57                 regulator-name = "3P3V";
  58                 regulator-min-microvolt = <3300000>;
  59                 regulator-max-microvolt = <3300000>;
  60                 regulator-boot-on;
  61                 regulator-always-on;
  62         };
  63 };
  64
  65 &can1 {
  66         pinctrl-names = "default";
  67         pinctrl-0 = <&pinctrl_flexcan1>;
  68         xceiver-supply = <&reg_3p3v>;
  69 };
  70
  71 &can2 {
  72         pinctrl-names = "default";
  73         pinctrl-0 = <&pinctrl_flexcan2>;
  74         xceiver-supply = <&reg_3p3v>;
  75 };
  76
  77 &clks {
  78         assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>;
  79         assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
  80 };
  81
  82 &fec {
  83         pinctrl-names = "default";
  84         pinctrl-0 = <&pinctrl_enet>;
  85         phy-reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
  86         phy-mode = "rmii";
  87         status = "okay";
  88 };
  89
  90 &gpmi {
  91         pinctrl-names = "default";
  92         pinctrl-0 = <&pinctrl_gpmi_nand>;
  93         nand-on-flash-bbt;
  94         status = "okay";
  95 };
  96
  97 &i2c1 {
  98         clock-frequency = <100000>;
  99         pinctrl-names = "default";
 100         pinctrl-0 = <&pinctrl_i2c1>;
 101         status = "okay";
 102 };
 103
 104 &i2c2 {
 105         clock-frequency = <100000>;
 106         pinctrl-names = "default";
 107         pinctrl-0 = <&pinctrl_i2c2>;
 108         status = "okay";
 109 };
 110
 111 &i2c3 {
 112         clock-frequency = <100000>;
 113         pinctrl-names = "default";
 114         pinctrl-0 = <&pinctrl_i2c3>;
 115         status = "okay";
 116 };
 117
 118 &uart4 {
 119         pinctrl-names = "default";
 120         pinctrl-0 = <&pinctrl_uart4>;
 121         status = "okay";
 122 };
 123
 124 &usdhc1 {
 125         pinctrl-names = "default";
 126         pinctrl-0 = <&pinctrl_usdhc1>;
 127         cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
 128         no-1-8-v;
 129         status = "okay";
 130 };
 131
 132 &usdhc3 {
 133         pinctrl-names = "default";
 134         pinctrl-0 = <&pinctrl_usdhc3>;
 135         no-1-8-v;
 136         non-removable;
 137         status = "disabled";
 138 };
 139
 140 &iomuxc {
 141         pinctrl_enet: enetgrp {
 142                 fsl,pins = <
 143                         MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x1b0b0
 144                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x1b0b1
 145                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
 146                         MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x1b0b0
 147                         MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x1b0b0
 148                         MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x1b0b0
 149                         MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x1b0b0
 150                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 151                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 152                         MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23     0x1b0b0
 153                         MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x1b0b0
 154                 >;
 155         };
 156
 157         pinctrl_flexcan1: flexcan1grp {
 158                 fsl,pins = <
 159                         MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020
 160                         MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020
 161                 >;
 162         };
 163
 164         pinctrl_flexcan2: flexcan2grp {
 165                 fsl,pins = <
 166                         MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020
 167                         MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020
 168                 >;
 169         };
 170
 171         pinctrl_gpmi_nand: gpmi-nand {
 172                 fsl,pins = <
 173                         MX6QDL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
 174                         MX6QDL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
 175                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
 176                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
 177                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
 178                         MX6QDL_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
 179                         MX6QDL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
 180                         MX6QDL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
 181                         MX6QDL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
 182                         MX6QDL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
 183                         MX6QDL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
 184                         MX6QDL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
 185                         MX6QDL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
 186                         MX6QDL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
 187                         MX6QDL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
 188                         MX6QDL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
 189                         MX6QDL_PAD_SD4_DAT0__NAND_DQS      0x00b1
 190                 >;
 191         };
 192
 193         pinctrl_i2c1: i2c1grp {
 194                 fsl,pins = <
 195                         MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
 196                         MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
 197                 >;
 198         };
 199
 200         pinctrl_i2c2: i2c2grp {
 201                 fsl,pins = <
 202                         MX6QDL_PAD_EIM_EB2__I2C2_SCL  0x4001b8b1
 203                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
 204                 >;
 205         };
 206
 207         pinctrl_i2c3: i2c3grp {
 208                 fsl,pins = <
 209                         MX6QDL_PAD_GPIO_5__I2C3_SCL  0x4001b8b1
 210                         MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
 211                         MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0
 212                 >;
 213         };
 214
 215         pinctrl_uart4: uart4grp {
 216                 fsl,pins = <
 217                         MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
 218                         MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
 219                 >;
 220         };
 221
 222         pinctrl_usdhc1: usdhc1grp {
 223                 fsl,pins = <
 224                         MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17070
 225                         MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10070
 226                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17070
 227                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17070
 228                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17070
 229                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17070
 230                 >;
 231         };
 232
 233         pinctrl_usdhc3: usdhc3grp {
 234                 fsl,pins = <
 235                         MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059
 236                         MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10059
 237                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
 238                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
 239                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
 240                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
 241                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
 242                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
 243                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
 244                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
 245                 >;
 246         };
 247 };