arch/arm/dts/imx6q.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright 2013 Freescale Semiconductor, Inc.
   4
   5 #include <dt-bindings/interrupt-controller/irq.h>
   6 #include "imx6q-pinfunc.h"
   7 #include "imx6qdl.dtsi"
   8
   9 / {
  10         aliases {
  11                 ipu1 = &ipu2;
  12                 spi4 = &ecspi5;
  13         };
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu0: cpu@0 {
  20                         compatible = "arm,cortex-a9";
  21                         device_type = "cpu";
  22                         reg = <0>;
  23                         next-level-cache = <&L2>;
  24                         operating-points = <
  25                                 /* kHz    uV */
  26                                 1200000 1275000
  27                                 996000  1250000
  28                                 852000  1250000
  29                                 792000  1175000
  30                                 396000  975000
  31                         >;
  32                         fsl,soc-operating-points = <
  33                                 /* ARM kHz  SOC-PU uV */
  34                                 1200000 1275000
  35                                 996000  1250000
  36                                 852000  1250000
  37                                 792000  1175000
  38                                 396000  1175000
  39                         >;
  40                         clock-latency = <61036>; /* two CLK32 periods */
  41                         #cooling-cells = <2>;
  42                         clocks = <&clks IMX6QDL_CLK_ARM>,
  43                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
  44                                  <&clks IMX6QDL_CLK_STEP>,
  45                                  <&clks IMX6QDL_CLK_PLL1_SW>,
  46                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
  47                         clock-names = "arm", "pll2_pfd2_396m", "step",
  48                                       "pll1_sw", "pll1_sys";
  49                         arm-supply = <&reg_arm>;
  50                         pu-supply = <&reg_pu>;
  51                         soc-supply = <&reg_soc>;
  52                 };
  53
  54                 cpu1: cpu@1 {
  55                         compatible = "arm,cortex-a9";
  56                         device_type = "cpu";
  57                         reg = <1>;
  58                         next-level-cache = <&L2>;
  59                         operating-points = <
  60                                 /* kHz    uV */
  61                                 1200000 1275000
  62                                 996000  1250000
  63                                 852000  1250000
  64                                 792000  1175000
  65                                 396000  975000
  66                         >;
  67                         fsl,soc-operating-points = <
  68                                 /* ARM kHz  SOC-PU uV */
  69                                 1200000 1275000
  70                                 996000  1250000
  71                                 852000  1250000
  72                                 792000  1175000
  73                                 396000  1175000
  74                         >;
  75                         clock-latency = <61036>; /* two CLK32 periods */
  76                         clocks = <&clks IMX6QDL_CLK_ARM>,
  77                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
  78                                  <&clks IMX6QDL_CLK_STEP>,
  79                                  <&clks IMX6QDL_CLK_PLL1_SW>,
  80                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
  81                         clock-names = "arm", "pll2_pfd2_396m", "step",
  82                                       "pll1_sw", "pll1_sys";
  83                         arm-supply = <&reg_arm>;
  84                         pu-supply = <&reg_pu>;
  85                         soc-supply = <&reg_soc>;
  86                 };
  87
  88                 cpu2: cpu@2 {
  89                         compatible = "arm,cortex-a9";
  90                         device_type = "cpu";
  91                         reg = <2>;
  92                         next-level-cache = <&L2>;
  93                         operating-points = <
  94                                 /* kHz    uV */
  95                                 1200000 1275000
  96                                 996000  1250000
  97                                 852000  1250000
  98                                 792000  1175000
  99                                 396000  975000
 100                         >;
 101                         fsl,soc-operating-points = <
 102                                 /* ARM kHz  SOC-PU uV */
 103                                 1200000 1275000
 104                                 996000  1250000
 105                                 852000  1250000
 106                                 792000  1175000
 107                                 396000  1175000
 108                         >;
 109                         clock-latency = <61036>; /* two CLK32 periods */
 110                         clocks = <&clks IMX6QDL_CLK_ARM>,
 111                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
 112                                  <&clks IMX6QDL_CLK_STEP>,
 113                                  <&clks IMX6QDL_CLK_PLL1_SW>,
 114                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
 115                         clock-names = "arm", "pll2_pfd2_396m", "step",
 116                                       "pll1_sw", "pll1_sys";
 117                         arm-supply = <&reg_arm>;
 118                         pu-supply = <&reg_pu>;
 119                         soc-supply = <&reg_soc>;
 120                 };
 121
 122                 cpu3: cpu@3 {
 123                         compatible = "arm,cortex-a9";
 124                         device_type = "cpu";
 125                         reg = <3>;
 126                         next-level-cache = <&L2>;
 127                         operating-points = <
 128                                 /* kHz    uV */
 129                                 1200000 1275000
 130                                 996000  1250000
 131                                 852000  1250000
 132                                 792000  1175000
 133                                 396000  975000
 134                         >;
 135                         fsl,soc-operating-points = <
 136                                 /* ARM kHz  SOC-PU uV */
 137                                 1200000 1275000
 138                                 996000  1250000
 139                                 852000  1250000
 140                                 792000  1175000
 141                                 396000  1175000
 142                         >;
 143                         clock-latency = <61036>; /* two CLK32 periods */
 144                         clocks = <&clks IMX6QDL_CLK_ARM>,
 145                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
 146                                  <&clks IMX6QDL_CLK_STEP>,
 147                                  <&clks IMX6QDL_CLK_PLL1_SW>,
 148                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
 149                         clock-names = "arm", "pll2_pfd2_396m", "step",
 150                                       "pll1_sw", "pll1_sys";
 151                         arm-supply = <&reg_arm>;
 152                         pu-supply = <&reg_pu>;
 153                         soc-supply = <&reg_soc>;
 154                 };
 155         };
 156
 157         soc {
 158                 ocram: sram@900000 {
 159                         compatible = "mmio-sram";
 160                         reg = <0x00900000 0x40000>;
 161                         clocks = <&clks IMX6QDL_CLK_OCRAM>;
 162                 };
 163
 164                 aips-bus@2000000 { /* AIPS1 */
 165                         spba-bus@2000000 {
 166                                 ecspi5: spi@2018000 {
 167                                         #address-cells = <1>;
 168                                         #size-cells = <0>;
 169                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 170                                         reg = <0x02018000 0x4000>;
 171                                         interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
 172                                         clocks = <&clks IMX6Q_CLK_ECSPI5>,
 173                                                  <&clks IMX6Q_CLK_ECSPI5>;
 174                                         clock-names = "ipg", "per";
 175                                         dmas = <&sdma 11 8 1>, <&sdma 12 8 2>;
 176                                         dma-names = "rx", "tx";
 177                                         status = "disabled";
 178                                 };
 179                         };
 180
 181                         iomuxc: iomuxc@20e0000 {
 182                                 compatible = "fsl,imx6q-iomuxc";
 183                         };
 184                 };
 185
 186                 sata: sata@2200000 {
 187                         compatible = "fsl,imx6q-ahci";
 188                         reg = <0x02200000 0x4000>;
 189                         interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
 190                         clocks = <&clks IMX6QDL_CLK_SATA>,
 191                                  <&clks IMX6QDL_CLK_SATA_REF_100M>,
 192                                  <&clks IMX6QDL_CLK_AHB>;
 193                         clock-names = "sata", "sata_ref", "ahb";
 194                         status = "disabled";
 195                 };
 196
 197                 gpu_vg: gpu@2204000 {
 198                         compatible = "vivante,gc";
 199                         reg = <0x02204000 0x4000>;
 200                         interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 201                         clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
 202                                  <&clks IMX6QDL_CLK_GPU2D_CORE>;
 203                         clock-names = "bus", "core";
 204                         power-domains = <&pd_pu>;
 205                 };
 206
 207                 ipu2: ipu@2800000 {
 208                         #address-cells = <1>;
 209                         #size-cells = <0>;
 210                         compatible = "fsl,imx6q-ipu";
 211                         reg = <0x02800000 0x400000>;
 212                         interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
 213                                      <0 7 IRQ_TYPE_LEVEL_HIGH>;
 214                         clocks = <&clks IMX6QDL_CLK_IPU2>,
 215                                  <&clks IMX6QDL_CLK_IPU2_DI0>,
 216                                  <&clks IMX6QDL_CLK_IPU2_DI1>;
 217                         clock-names = "bus", "di0", "di1";
 218                         resets = <&src 4>;
 219
 220                         ipu2_csi0: port@0 {
 221                                 reg = <0>;
 222
 223                                 ipu2_csi0_from_mipi_vc2: endpoint {
 224                                         remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
 225                                 };
 226                         };
 227
 228                         ipu2_csi1: port@1 {
 229                                 reg = <1>;
 230
 231                                 ipu2_csi1_from_ipu2_csi1_mux: endpoint {
 232                                         remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
 233                                 };
 234                         };
 235
 236                         ipu2_di0: port@2 {
 237                                 reg = <2>;
 238
 239                                 ipu2_di0_disp0: endpoint@0 {
 240                                         reg = <0>;
 241                                 };
 242
 243                                 ipu2_di0_hdmi: endpoint@1 {
 244                                         reg = <1>;
 245                                         remote-endpoint = <&hdmi_mux_2>;
 246                                 };
 247
 248                                 ipu2_di0_mipi: endpoint@2 {
 249                                         reg = <2>;
 250                                         remote-endpoint = <&mipi_mux_2>;
 251                                 };
 252
 253                                 ipu2_di0_lvds0: endpoint@3 {
 254                                         reg = <3>;
 255                                         remote-endpoint = <&lvds0_mux_2>;
 256                                 };
 257
 258                                 ipu2_di0_lvds1: endpoint@4 {
 259                                         reg = <4>;
 260                                         remote-endpoint = <&lvds1_mux_2>;
 261                                 };
 262                         };
 263
 264                         ipu2_di1: port@3 {
 265                                 reg = <3>;
 266
 267                                 ipu2_di1_hdmi: endpoint@1 {
 268                                         reg = <1>;
 269                                         remote-endpoint = <&hdmi_mux_3>;
 270                                 };
 271
 272                                 ipu2_di1_mipi: endpoint@2 {
 273                                         reg = <2>;
 274                                         remote-endpoint = <&mipi_mux_3>;
 275                                 };
 276
 277                                 ipu2_di1_lvds0: endpoint@3 {
 278                                         reg = <3>;
 279                                         remote-endpoint = <&lvds0_mux_3>;
 280                                 };
 281
 282                                 ipu2_di1_lvds1: endpoint@4 {
 283                                         reg = <4>;
 284                                         remote-endpoint = <&lvds1_mux_3>;
 285                                 };
 286                         };
 287                 };
 288         };
 289
 290         capture-subsystem {
 291                 compatible = "fsl,imx-capture-subsystem";
 292                 ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>;
 293         };
 294
 295         display-subsystem {
 296                 compatible = "fsl,imx-display-subsystem";
 297                 ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
 298         };
 299 };
 300
 301 &gpio1 {
 302         gpio-ranges = <&iomuxc  0 136  2>, <&iomuxc  2 141 1>, <&iomuxc  3 139 1>,
 303                       <&iomuxc  4 142  2>, <&iomuxc  6 140 1>, <&iomuxc  7 144 2>,
 304                       <&iomuxc  9 138  1>, <&iomuxc 10 213 3>, <&iomuxc 13  20 1>,
 305                       <&iomuxc 14  19  1>, <&iomuxc 15  21 1>, <&iomuxc 16 208 1>,
 306                       <&iomuxc 17 207  1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,
 307                       <&iomuxc 22 116 10>;
 308 };
 309
 310 &gpio2 {
 311         gpio-ranges = <&iomuxc  0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
 312                       <&iomuxc 31  44  1>;
 313 };
 314
 315 &gpio3 {
 316         gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
 317 };
 318
 319 &gpio4 {
 320         gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
 321 };
 322
 323 &gpio5 {
 324         gpio-ranges = <&iomuxc 0  85  1>, <&iomuxc  2  34  1>, <&iomuxc 4 53 1>,
 325                       <&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
 326 };
 327
 328 &gpio6 {
 329         gpio-ranges = <&iomuxc  0 164 6>, <&iomuxc  6  54 1>, <&iomuxc  7 181  5>,
 330                       <&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19  22 12>,
 331                       <&iomuxc 31  86 1>;
 332 };
 333
 334 &gpio7 {
 335         gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
 336 };
 337
 338 &gpr {
 339         ipu1_csi0_mux {
 340                 compatible = "video-mux";
 341                 mux-controls = <&mux 0>;
 342                 #address-cells = <1>;
 343                 #size-cells = <0>;
 344
 345                 port@0 {
 346                         reg = <0>;
 347
 348                         ipu1_csi0_mux_from_mipi_vc0: endpoint {
 349                                 remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
 350                         };
 351                 };
 352
 353                 port@1 {
 354                         reg = <1>;
 355
 356                         ipu1_csi0_mux_from_parallel_sensor: endpoint {
 357                         };
 358                 };
 359
 360                 port@2 {
 361                         reg = <2>;
 362
 363                         ipu1_csi0_mux_to_ipu1_csi0: endpoint {
 364                                 remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
 365                         };
 366                 };
 367         };
 368
 369         ipu2_csi1_mux {
 370                 compatible = "video-mux";
 371                 mux-controls = <&mux 1>;
 372                 #address-cells = <1>;
 373                 #size-cells = <0>;
 374
 375                 port@0 {
 376                         reg = <0>;
 377
 378                         ipu2_csi1_mux_from_mipi_vc3: endpoint {
 379                                 remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
 380                         };
 381                 };
 382
 383                 port@1 {
 384                         reg = <1>;
 385
 386                         ipu2_csi1_mux_from_parallel_sensor: endpoint {
 387                         };
 388                 };
 389
 390                 port@2 {
 391                         reg = <2>;
 392
 393                         ipu2_csi1_mux_to_ipu2_csi1: endpoint {
 394                                 remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
 395                         };
 396                 };
 397         };
 398 };
 399
 400 &hdmi {
 401         compatible = "fsl,imx6q-hdmi";
 402
 403         port@2 {
 404                 reg = <2>;
 405
 406                 hdmi_mux_2: endpoint {
 407                         remote-endpoint = <&ipu2_di0_hdmi>;
 408                 };
 409         };
 410
 411         port@3 {
 412                 reg = <3>;
 413
 414                 hdmi_mux_3: endpoint {
 415                         remote-endpoint = <&ipu2_di1_hdmi>;
 416                 };
 417         };
 418 };
 419
 420 &ipu1_csi1 {
 421         ipu1_csi1_from_mipi_vc1: endpoint {
 422                 remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
 423         };
 424 };
 425
 426 &ldb {
 427         clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
 428                  <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
 429                  <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
 430                  <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
 431         clock-names = "di0_pll", "di1_pll",
 432                       "di0_sel", "di1_sel", "di2_sel", "di3_sel",
 433                       "di0", "di1";
 434
 435         lvds-channel@0 {
 436                 port@2 {
 437                         reg = <2>;
 438
 439                         lvds0_mux_2: endpoint {
 440                                 remote-endpoint = <&ipu2_di0_lvds0>;
 441                         };
 442                 };
 443
 444                 port@3 {
 445                         reg = <3>;
 446
 447                         lvds0_mux_3: endpoint {
 448                                 remote-endpoint = <&ipu2_di1_lvds0>;
 449                         };
 450                 };
 451         };
 452
 453         lvds-channel@1 {
 454                 port@2 {
 455                         reg = <2>;
 456
 457                         lvds1_mux_2: endpoint {
 458                                 remote-endpoint = <&ipu2_di0_lvds1>;
 459                         };
 460                 };
 461
 462                 port@3 {
 463                         reg = <3>;
 464
 465                         lvds1_mux_3: endpoint {
 466                                 remote-endpoint = <&ipu2_di1_lvds1>;
 467                         };
 468                 };
 469         };
 470 };
 471
 472 &mipi_csi {
 473         port@1 {
 474                 reg = <1>;
 475
 476                 mipi_vc0_to_ipu1_csi0_mux: endpoint {
 477                         remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
 478                 };
 479         };
 480
 481         port@2 {
 482                 reg = <2>;
 483
 484                 mipi_vc1_to_ipu1_csi1: endpoint {
 485                         remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
 486                 };
 487         };
 488
 489         port@3 {
 490                 reg = <3>;
 491
 492                 mipi_vc2_to_ipu2_csi0: endpoint {
 493                         remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
 494                 };
 495         };
 496
 497         port@4 {
 498                 reg = <4>;
 499
 500                 mipi_vc3_to_ipu2_csi1_mux: endpoint {
 501                         remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
 502                 };
 503         };
 504 };
 505
 506 &mipi_dsi {
 507         ports {
 508                 port@2 {
 509                         reg = <2>;
 510
 511                         mipi_mux_2: endpoint {
 512                                 remote-endpoint = <&ipu2_di0_mipi>;
 513                         };
 514                 };
 515
 516                 port@3 {
 517                         reg = <3>;
 518
 519                         mipi_mux_3: endpoint {
 520                                 remote-endpoint = <&ipu2_di1_mipi>;
 521                         };
 522                 };
 523         };
 524 };
 525
 526 &mux {
 527         mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
 528                         <0x04 0x00100000>, /* MIPI_IPU2_MUX */
 529                         <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
 530                         <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
 531                         <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
 532                         <0x28 0x00000003>, /* DCIC1_MUX_CTL */
 533                         <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
 534 };
 535
 536 &vpu {
 537         compatible = "fsl,imx6q-vpu", "cnm,coda960";
 538 };