1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright 2013 Freescale Semiconductor, Inc.
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6q-pinfunc.h"
7 #include "imx6qdl.dtsi"
20 compatible = "arm,cortex-a9";
23 next-level-cache = <&L2>;
32 fsl,soc-operating-points = <
33 /* ARM kHz SOC-PU uV */
40 clock-latency = <61036>; /* two CLK32 periods */
42 clocks = <&clks IMX6QDL_CLK_ARM>,
43 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
44 <&clks IMX6QDL_CLK_STEP>,
45 <&clks IMX6QDL_CLK_PLL1_SW>,
46 <&clks IMX6QDL_CLK_PLL1_SYS>;
47 clock-names = "arm", "pll2_pfd2_396m", "step",
48 "pll1_sw", "pll1_sys";
49 arm-supply = <®_arm>;
50 pu-supply = <®_pu>;
51 soc-supply = <®_soc>;
55 compatible = "arm,cortex-a9";
58 next-level-cache = <&L2>;
67 fsl,soc-operating-points = <
68 /* ARM kHz SOC-PU uV */
75 clock-latency = <61036>; /* two CLK32 periods */
76 clocks = <&clks IMX6QDL_CLK_ARM>,
77 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
78 <&clks IMX6QDL_CLK_STEP>,
79 <&clks IMX6QDL_CLK_PLL1_SW>,
80 <&clks IMX6QDL_CLK_PLL1_SYS>;
81 clock-names = "arm", "pll2_pfd2_396m", "step",
82 "pll1_sw", "pll1_sys";
83 arm-supply = <®_arm>;
84 pu-supply = <®_pu>;
85 soc-supply = <®_soc>;
89 compatible = "arm,cortex-a9";
92 next-level-cache = <&L2>;
101 fsl,soc-operating-points = <
102 /* ARM kHz SOC-PU uV */
109 clock-latency = <61036>; /* two CLK32 periods */
110 clocks = <&clks IMX6QDL_CLK_ARM>,
111 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
112 <&clks IMX6QDL_CLK_STEP>,
113 <&clks IMX6QDL_CLK_PLL1_SW>,
114 <&clks IMX6QDL_CLK_PLL1_SYS>;
115 clock-names = "arm", "pll2_pfd2_396m", "step",
116 "pll1_sw", "pll1_sys";
117 arm-supply = <®_arm>;
118 pu-supply = <®_pu>;
119 soc-supply = <®_soc>;
123 compatible = "arm,cortex-a9";
126 next-level-cache = <&L2>;
135 fsl,soc-operating-points = <
136 /* ARM kHz SOC-PU uV */
143 clock-latency = <61036>; /* two CLK32 periods */
144 clocks = <&clks IMX6QDL_CLK_ARM>,
145 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
146 <&clks IMX6QDL_CLK_STEP>,
147 <&clks IMX6QDL_CLK_PLL1_SW>,
148 <&clks IMX6QDL_CLK_PLL1_SYS>;
149 clock-names = "arm", "pll2_pfd2_396m", "step",
150 "pll1_sw", "pll1_sys";
151 arm-supply = <®_arm>;
152 pu-supply = <®_pu>;
153 soc-supply = <®_soc>;
159 compatible = "mmio-sram";
160 reg = <0x00900000 0x40000>;
161 clocks = <&clks IMX6QDL_CLK_OCRAM>;
164 aips-bus@2000000 { /* AIPS1 */
166 ecspi5: spi@2018000 {
167 #address-cells = <1>;
169 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
170 reg = <0x02018000 0x4000>;
171 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
172 clocks = <&clks IMX6Q_CLK_ECSPI5>,
173 <&clks IMX6Q_CLK_ECSPI5>;
174 clock-names = "ipg", "per";
175 dmas = <&sdma 11 8 1>, <&sdma 12 8 2>;
176 dma-names = "rx", "tx";
181 iomuxc: iomuxc@20e0000 {
182 compatible = "fsl,imx6q-iomuxc";
187 compatible = "fsl,imx6q-ahci";
188 reg = <0x02200000 0x4000>;
189 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
190 clocks = <&clks IMX6QDL_CLK_SATA>,
191 <&clks IMX6QDL_CLK_SATA_REF_100M>,
192 <&clks IMX6QDL_CLK_AHB>;
193 clock-names = "sata", "sata_ref", "ahb";
197 gpu_vg: gpu@2204000 {
198 compatible = "vivante,gc";
199 reg = <0x02204000 0x4000>;
200 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
201 clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
202 <&clks IMX6QDL_CLK_GPU2D_CORE>;
203 clock-names = "bus", "core";
204 power-domains = <&pd_pu>;
208 #address-cells = <1>;
210 compatible = "fsl,imx6q-ipu";
211 reg = <0x02800000 0x400000>;
212 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
213 <0 7 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&clks IMX6QDL_CLK_IPU2>,
215 <&clks IMX6QDL_CLK_IPU2_DI0>,
216 <&clks IMX6QDL_CLK_IPU2_DI1>;
217 clock-names = "bus", "di0", "di1";
223 ipu2_csi0_from_mipi_vc2: endpoint {
224 remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
231 ipu2_csi1_from_ipu2_csi1_mux: endpoint {
232 remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
239 ipu2_di0_disp0: endpoint@0 {
243 ipu2_di0_hdmi: endpoint@1 {
245 remote-endpoint = <&hdmi_mux_2>;
248 ipu2_di0_mipi: endpoint@2 {
250 remote-endpoint = <&mipi_mux_2>;
253 ipu2_di0_lvds0: endpoint@3 {
255 remote-endpoint = <&lvds0_mux_2>;
258 ipu2_di0_lvds1: endpoint@4 {
260 remote-endpoint = <&lvds1_mux_2>;
267 ipu2_di1_hdmi: endpoint@1 {
269 remote-endpoint = <&hdmi_mux_3>;
272 ipu2_di1_mipi: endpoint@2 {
274 remote-endpoint = <&mipi_mux_3>;
277 ipu2_di1_lvds0: endpoint@3 {
279 remote-endpoint = <&lvds0_mux_3>;
282 ipu2_di1_lvds1: endpoint@4 {
284 remote-endpoint = <&lvds1_mux_3>;
291 compatible = "fsl,imx-capture-subsystem";
292 ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>;
296 compatible = "fsl,imx-display-subsystem";
297 ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
302 gpio-ranges = <&iomuxc 0 136 2>, <&iomuxc 2 141 1>, <&iomuxc 3 139 1>,
303 <&iomuxc 4 142 2>, <&iomuxc 6 140 1>, <&iomuxc 7 144 2>,
304 <&iomuxc 9 138 1>, <&iomuxc 10 213 3>, <&iomuxc 13 20 1>,
305 <&iomuxc 14 19 1>, <&iomuxc 15 21 1>, <&iomuxc 16 208 1>,
306 <&iomuxc 17 207 1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,
311 gpio-ranges = <&iomuxc 0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
316 gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
320 gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
324 gpio-ranges = <&iomuxc 0 85 1>, <&iomuxc 2 34 1>, <&iomuxc 4 53 1>,
325 <&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
329 gpio-ranges = <&iomuxc 0 164 6>, <&iomuxc 6 54 1>, <&iomuxc 7 181 5>,
330 <&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19 22 12>,
335 gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
340 compatible = "video-mux";
341 mux-controls = <&mux 0>;
342 #address-cells = <1>;
348 ipu1_csi0_mux_from_mipi_vc0: endpoint {
349 remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
356 ipu1_csi0_mux_from_parallel_sensor: endpoint {
363 ipu1_csi0_mux_to_ipu1_csi0: endpoint {
364 remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
370 compatible = "video-mux";
371 mux-controls = <&mux 1>;
372 #address-cells = <1>;
378 ipu2_csi1_mux_from_mipi_vc3: endpoint {
379 remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
386 ipu2_csi1_mux_from_parallel_sensor: endpoint {
393 ipu2_csi1_mux_to_ipu2_csi1: endpoint {
394 remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
401 compatible = "fsl,imx6q-hdmi";
406 hdmi_mux_2: endpoint {
407 remote-endpoint = <&ipu2_di0_hdmi>;
414 hdmi_mux_3: endpoint {
415 remote-endpoint = <&ipu2_di1_hdmi>;
421 ipu1_csi1_from_mipi_vc1: endpoint {
422 remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
427 clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
428 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
429 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
430 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
431 clock-names = "di0_pll", "di1_pll",
432 "di0_sel", "di1_sel", "di2_sel", "di3_sel",
439 lvds0_mux_2: endpoint {
440 remote-endpoint = <&ipu2_di0_lvds0>;
447 lvds0_mux_3: endpoint {
448 remote-endpoint = <&ipu2_di1_lvds0>;
457 lvds1_mux_2: endpoint {
458 remote-endpoint = <&ipu2_di0_lvds1>;
465 lvds1_mux_3: endpoint {
466 remote-endpoint = <&ipu2_di1_lvds1>;
476 mipi_vc0_to_ipu1_csi0_mux: endpoint {
477 remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
484 mipi_vc1_to_ipu1_csi1: endpoint {
485 remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
492 mipi_vc2_to_ipu2_csi0: endpoint {
493 remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
500 mipi_vc3_to_ipu2_csi1_mux: endpoint {
501 remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
511 mipi_mux_2: endpoint {
512 remote-endpoint = <&ipu2_di0_mipi>;
519 mipi_mux_3: endpoint {
520 remote-endpoint = <&ipu2_di1_mipi>;
527 mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
528 <0x04 0x00100000>, /* MIPI_IPU2_MUX */
529 <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
530 <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
531 <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
532 <0x28 0x00000003>, /* DCIC1_MUX_CTL */
533 <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
537 compatible = "fsl,imx6q-vpu", "cnm,coda960";