1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright 2013 Freescale Semiconductor, Inc.
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6q-pinfunc.h"
7 #include "imx6qdl.dtsi"
21 compatible = "arm,cortex-a9";
24 next-level-cache = <&L2>;
33 fsl,soc-operating-points = <
34 /* ARM kHz SOC-PU uV */
41 clock-latency = <61036>; /* two CLK32 periods */
43 clocks = <&clks IMX6QDL_CLK_ARM>,
44 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
45 <&clks IMX6QDL_CLK_STEP>,
46 <&clks IMX6QDL_CLK_PLL1_SW>,
47 <&clks IMX6QDL_CLK_PLL1_SYS>;
48 clock-names = "arm", "pll2_pfd2_396m", "step",
49 "pll1_sw", "pll1_sys";
50 arm-supply = <®_arm>;
51 pu-supply = <®_pu>;
52 soc-supply = <®_soc>;
56 compatible = "arm,cortex-a9";
59 next-level-cache = <&L2>;
68 fsl,soc-operating-points = <
69 /* ARM kHz SOC-PU uV */
76 clock-latency = <61036>; /* two CLK32 periods */
77 clocks = <&clks IMX6QDL_CLK_ARM>,
78 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
79 <&clks IMX6QDL_CLK_STEP>,
80 <&clks IMX6QDL_CLK_PLL1_SW>,
81 <&clks IMX6QDL_CLK_PLL1_SYS>;
82 clock-names = "arm", "pll2_pfd2_396m", "step",
83 "pll1_sw", "pll1_sys";
84 arm-supply = <®_arm>;
85 pu-supply = <®_pu>;
86 soc-supply = <®_soc>;
90 compatible = "arm,cortex-a9";
93 next-level-cache = <&L2>;
102 fsl,soc-operating-points = <
103 /* ARM kHz SOC-PU uV */
110 clock-latency = <61036>; /* two CLK32 periods */
111 clocks = <&clks IMX6QDL_CLK_ARM>,
112 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
113 <&clks IMX6QDL_CLK_STEP>,
114 <&clks IMX6QDL_CLK_PLL1_SW>,
115 <&clks IMX6QDL_CLK_PLL1_SYS>;
116 clock-names = "arm", "pll2_pfd2_396m", "step",
117 "pll1_sw", "pll1_sys";
118 arm-supply = <®_arm>;
119 pu-supply = <®_pu>;
120 soc-supply = <®_soc>;
124 compatible = "arm,cortex-a9";
127 next-level-cache = <&L2>;
136 fsl,soc-operating-points = <
137 /* ARM kHz SOC-PU uV */
144 clock-latency = <61036>; /* two CLK32 periods */
145 clocks = <&clks IMX6QDL_CLK_ARM>,
146 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
147 <&clks IMX6QDL_CLK_STEP>,
148 <&clks IMX6QDL_CLK_PLL1_SW>,
149 <&clks IMX6QDL_CLK_PLL1_SYS>;
150 clock-names = "arm", "pll2_pfd2_396m", "step",
151 "pll1_sw", "pll1_sys";
152 arm-supply = <®_arm>;
153 pu-supply = <®_pu>;
154 soc-supply = <®_soc>;
160 compatible = "mmio-sram";
161 reg = <0x00900000 0x40000>;
162 clocks = <&clks IMX6QDL_CLK_OCRAM>;
165 aips-bus@2000000 { /* AIPS1 */
167 ecspi5: spi@2018000 {
168 #address-cells = <1>;
170 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
171 reg = <0x02018000 0x4000>;
172 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
173 clocks = <&clks IMX6Q_CLK_ECSPI5>,
174 <&clks IMX6Q_CLK_ECSPI5>;
175 clock-names = "ipg", "per";
176 dmas = <&sdma 11 8 1>, <&sdma 12 8 2>;
177 dma-names = "rx", "tx";
182 iomuxc: iomuxc@20e0000 {
183 compatible = "fsl,imx6q-iomuxc";
188 compatible = "fsl,imx6q-ahci";
189 reg = <0x02200000 0x4000>;
190 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
191 clocks = <&clks IMX6QDL_CLK_SATA>,
192 <&clks IMX6QDL_CLK_SATA_REF_100M>,
193 <&clks IMX6QDL_CLK_AHB>;
194 clock-names = "sata", "sata_ref", "ahb";
198 gpu_vg: gpu@2204000 {
199 compatible = "vivante,gc";
200 reg = <0x02204000 0x4000>;
201 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
202 clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
203 <&clks IMX6QDL_CLK_GPU2D_CORE>;
204 clock-names = "bus", "core";
205 power-domains = <&pd_pu>;
206 #cooling-cells = <2>;
210 #address-cells = <1>;
212 compatible = "fsl,imx6q-ipu";
213 reg = <0x02800000 0x400000>;
214 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
215 <0 7 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&clks IMX6QDL_CLK_IPU2>,
217 <&clks IMX6QDL_CLK_IPU2_DI0>,
218 <&clks IMX6QDL_CLK_IPU2_DI1>;
219 clock-names = "bus", "di0", "di1";
225 ipu2_csi0_from_mipi_vc2: endpoint {
226 remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
233 ipu2_csi1_from_ipu2_csi1_mux: endpoint {
234 remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
239 #address-cells = <1>;
243 ipu2_di0_disp0: endpoint@0 {
247 ipu2_di0_hdmi: endpoint@1 {
249 remote-endpoint = <&hdmi_mux_2>;
252 ipu2_di0_mipi: endpoint@2 {
254 remote-endpoint = <&mipi_mux_2>;
257 ipu2_di0_lvds0: endpoint@3 {
259 remote-endpoint = <&lvds0_mux_2>;
262 ipu2_di0_lvds1: endpoint@4 {
264 remote-endpoint = <&lvds1_mux_2>;
269 #address-cells = <1>;
273 ipu2_di1_hdmi: endpoint@1 {
275 remote-endpoint = <&hdmi_mux_3>;
278 ipu2_di1_mipi: endpoint@2 {
280 remote-endpoint = <&mipi_mux_3>;
283 ipu2_di1_lvds0: endpoint@3 {
285 remote-endpoint = <&lvds0_mux_3>;
288 ipu2_di1_lvds1: endpoint@4 {
290 remote-endpoint = <&lvds1_mux_3>;
297 compatible = "fsl,imx-capture-subsystem";
298 ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>;
302 compatible = "fsl,imx-display-subsystem";
303 ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
308 gpio-ranges = <&iomuxc 0 136 2>, <&iomuxc 2 141 1>, <&iomuxc 3 139 1>,
309 <&iomuxc 4 142 2>, <&iomuxc 6 140 1>, <&iomuxc 7 144 2>,
310 <&iomuxc 9 138 1>, <&iomuxc 10 213 3>, <&iomuxc 13 20 1>,
311 <&iomuxc 14 19 1>, <&iomuxc 15 21 1>, <&iomuxc 16 208 1>,
312 <&iomuxc 17 207 1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,
317 gpio-ranges = <&iomuxc 0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
322 gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
326 gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
330 gpio-ranges = <&iomuxc 0 85 1>, <&iomuxc 2 34 1>, <&iomuxc 4 53 1>,
331 <&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
335 gpio-ranges = <&iomuxc 0 164 6>, <&iomuxc 6 54 1>, <&iomuxc 7 181 5>,
336 <&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19 22 12>,
341 gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
346 compatible = "video-mux";
347 mux-controls = <&mux 0>;
348 #address-cells = <1>;
354 ipu1_csi0_mux_from_mipi_vc0: endpoint {
355 remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
362 ipu1_csi0_mux_from_parallel_sensor: endpoint {
369 ipu1_csi0_mux_to_ipu1_csi0: endpoint {
370 remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
376 compatible = "video-mux";
377 mux-controls = <&mux 1>;
378 #address-cells = <1>;
384 ipu2_csi1_mux_from_mipi_vc3: endpoint {
385 remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
392 ipu2_csi1_mux_from_parallel_sensor: endpoint {
399 ipu2_csi1_mux_to_ipu2_csi1: endpoint {
400 remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
407 compatible = "fsl,imx6q-hdmi";
412 hdmi_mux_2: endpoint {
413 remote-endpoint = <&ipu2_di0_hdmi>;
420 hdmi_mux_3: endpoint {
421 remote-endpoint = <&ipu2_di1_hdmi>;
427 ipu1_csi1_from_mipi_vc1: endpoint {
428 remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
433 clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
434 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
435 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
436 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
437 clock-names = "di0_pll", "di1_pll",
438 "di0_sel", "di1_sel", "di2_sel", "di3_sel",
445 lvds0_mux_2: endpoint {
446 remote-endpoint = <&ipu2_di0_lvds0>;
453 lvds0_mux_3: endpoint {
454 remote-endpoint = <&ipu2_di1_lvds0>;
463 lvds1_mux_2: endpoint {
464 remote-endpoint = <&ipu2_di0_lvds1>;
471 lvds1_mux_3: endpoint {
472 remote-endpoint = <&ipu2_di1_lvds1>;
482 mipi_vc0_to_ipu1_csi0_mux: endpoint {
483 remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
490 mipi_vc1_to_ipu1_csi1: endpoint {
491 remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
498 mipi_vc2_to_ipu2_csi0: endpoint {
499 remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
506 mipi_vc3_to_ipu2_csi1_mux: endpoint {
507 remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
517 mipi_mux_2: endpoint {
518 remote-endpoint = <&ipu2_di0_mipi>;
525 mipi_mux_3: endpoint {
526 remote-endpoint = <&ipu2_di1_mipi>;
533 mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
534 <0x04 0x00100000>, /* MIPI_IPU2_MUX */
535 <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
536 <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
537 <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
538 <0x28 0x00000003>, /* DCIC1_MUX_CTL */
539 <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
543 compatible = "fsl,imx6q-vpu", "cnm,coda960";