arch/arm/dts/imx6q.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright 2013 Freescale Semiconductor, Inc.
   4
   5 #include <dt-bindings/interrupt-controller/irq.h>
   6 #include "imx6q-pinfunc.h"
   7 #include "imx6qdl.dtsi"
   8
   9 / {
  10         aliases {
  11                 ipu1 = &ipu2;
  12                 video1 = &ipu2;
  13                 spi4 = &ecspi5;
  14         };
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu0: cpu@0 {
  21                         compatible = "arm,cortex-a9";
  22                         device_type = "cpu";
  23                         reg = <0>;
  24                         next-level-cache = <&L2>;
  25                         operating-points = <
  26                                 /* kHz    uV */
  27                                 1200000 1275000
  28                                 996000  1250000
  29                                 852000  1250000
  30                                 792000  1175000
  31                                 396000  975000
  32                         >;
  33                         fsl,soc-operating-points = <
  34                                 /* ARM kHz  SOC-PU uV */
  35                                 1200000 1275000
  36                                 996000  1250000
  37                                 852000  1250000
  38                                 792000  1175000
  39                                 396000  1175000
  40                         >;
  41                         clock-latency = <61036>; /* two CLK32 periods */
  42                         #cooling-cells = <2>;
  43                         clocks = <&clks IMX6QDL_CLK_ARM>,
  44                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
  45                                  <&clks IMX6QDL_CLK_STEP>,
  46                                  <&clks IMX6QDL_CLK_PLL1_SW>,
  47                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
  48                         clock-names = "arm", "pll2_pfd2_396m", "step",
  49                                       "pll1_sw", "pll1_sys";
  50                         arm-supply = <&reg_arm>;
  51                         pu-supply = <&reg_pu>;
  52                         soc-supply = <&reg_soc>;
  53                 };
  54
  55                 cpu1: cpu@1 {
  56                         compatible = "arm,cortex-a9";
  57                         device_type = "cpu";
  58                         reg = <1>;
  59                         next-level-cache = <&L2>;
  60                         operating-points = <
  61                                 /* kHz    uV */
  62                                 1200000 1275000
  63                                 996000  1250000
  64                                 852000  1250000
  65                                 792000  1175000
  66                                 396000  975000
  67                         >;
  68                         fsl,soc-operating-points = <
  69                                 /* ARM kHz  SOC-PU uV */
  70                                 1200000 1275000
  71                                 996000  1250000
  72                                 852000  1250000
  73                                 792000  1175000
  74                                 396000  1175000
  75                         >;
  76                         clock-latency = <61036>; /* two CLK32 periods */
  77                         clocks = <&clks IMX6QDL_CLK_ARM>,
  78                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
  79                                  <&clks IMX6QDL_CLK_STEP>,
  80                                  <&clks IMX6QDL_CLK_PLL1_SW>,
  81                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
  82                         clock-names = "arm", "pll2_pfd2_396m", "step",
  83                                       "pll1_sw", "pll1_sys";
  84                         arm-supply = <&reg_arm>;
  85                         pu-supply = <&reg_pu>;
  86                         soc-supply = <&reg_soc>;
  87                 };
  88
  89                 cpu2: cpu@2 {
  90                         compatible = "arm,cortex-a9";
  91                         device_type = "cpu";
  92                         reg = <2>;
  93                         next-level-cache = <&L2>;
  94                         operating-points = <
  95                                 /* kHz    uV */
  96                                 1200000 1275000
  97                                 996000  1250000
  98                                 852000  1250000
  99                                 792000  1175000
 100                                 396000  975000
 101                         >;
 102                         fsl,soc-operating-points = <
 103                                 /* ARM kHz  SOC-PU uV */
 104                                 1200000 1275000
 105                                 996000  1250000
 106                                 852000  1250000
 107                                 792000  1175000
 108                                 396000  1175000
 109                         >;
 110                         clock-latency = <61036>; /* two CLK32 periods */
 111                         clocks = <&clks IMX6QDL_CLK_ARM>,
 112                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
 113                                  <&clks IMX6QDL_CLK_STEP>,
 114                                  <&clks IMX6QDL_CLK_PLL1_SW>,
 115                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
 116                         clock-names = "arm", "pll2_pfd2_396m", "step",
 117                                       "pll1_sw", "pll1_sys";
 118                         arm-supply = <&reg_arm>;
 119                         pu-supply = <&reg_pu>;
 120                         soc-supply = <&reg_soc>;
 121                 };
 122
 123                 cpu3: cpu@3 {
 124                         compatible = "arm,cortex-a9";
 125                         device_type = "cpu";
 126                         reg = <3>;
 127                         next-level-cache = <&L2>;
 128                         operating-points = <
 129                                 /* kHz    uV */
 130                                 1200000 1275000
 131                                 996000  1250000
 132                                 852000  1250000
 133                                 792000  1175000
 134                                 396000  975000
 135                         >;
 136                         fsl,soc-operating-points = <
 137                                 /* ARM kHz  SOC-PU uV */
 138                                 1200000 1275000
 139                                 996000  1250000
 140                                 852000  1250000
 141                                 792000  1175000
 142                                 396000  1175000
 143                         >;
 144                         clock-latency = <61036>; /* two CLK32 periods */
 145                         clocks = <&clks IMX6QDL_CLK_ARM>,
 146                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
 147                                  <&clks IMX6QDL_CLK_STEP>,
 148                                  <&clks IMX6QDL_CLK_PLL1_SW>,
 149                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
 150                         clock-names = "arm", "pll2_pfd2_396m", "step",
 151                                       "pll1_sw", "pll1_sys";
 152                         arm-supply = <&reg_arm>;
 153                         pu-supply = <&reg_pu>;
 154                         soc-supply = <&reg_soc>;
 155                 };
 156         };
 157
 158         soc {
 159                 ocram: sram@900000 {
 160                         compatible = "mmio-sram";
 161                         reg = <0x00900000 0x40000>;
 162                         clocks = <&clks IMX6QDL_CLK_OCRAM>;
 163                 };
 164
 165                 aips-bus@2000000 { /* AIPS1 */
 166                         spba-bus@2000000 {
 167                                 ecspi5: spi@2018000 {
 168                                         #address-cells = <1>;
 169                                         #size-cells = <0>;
 170                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 171                                         reg = <0x02018000 0x4000>;
 172                                         interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
 173                                         clocks = <&clks IMX6Q_CLK_ECSPI5>,
 174                                                  <&clks IMX6Q_CLK_ECSPI5>;
 175                                         clock-names = "ipg", "per";
 176                                         dmas = <&sdma 11 8 1>, <&sdma 12 8 2>;
 177                                         dma-names = "rx", "tx";
 178                                         status = "disabled";
 179                                 };
 180                         };
 181
 182                         iomuxc: iomuxc@20e0000 {
 183                                 compatible = "fsl,imx6q-iomuxc";
 184                         };
 185                 };
 186
 187                 sata: sata@2200000 {
 188                         compatible = "fsl,imx6q-ahci";
 189                         reg = <0x02200000 0x4000>;
 190                         interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
 191                         clocks = <&clks IMX6QDL_CLK_SATA>,
 192                                  <&clks IMX6QDL_CLK_SATA_REF_100M>,
 193                                  <&clks IMX6QDL_CLK_AHB>;
 194                         clock-names = "sata", "sata_ref", "ahb";
 195                         status = "disabled";
 196                 };
 197
 198                 gpu_vg: gpu@2204000 {
 199                         compatible = "vivante,gc";
 200                         reg = <0x02204000 0x4000>;
 201                         interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 202                         clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
 203                                  <&clks IMX6QDL_CLK_GPU2D_CORE>;
 204                         clock-names = "bus", "core";
 205                         power-domains = <&pd_pu>;
 206                         #cooling-cells = <2>;
 207                 };
 208
 209                 ipu2: ipu@2800000 {
 210                         #address-cells = <1>;
 211                         #size-cells = <0>;
 212                         compatible = "fsl,imx6q-ipu";
 213                         reg = <0x02800000 0x400000>;
 214                         interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
 215                                      <0 7 IRQ_TYPE_LEVEL_HIGH>;
 216                         clocks = <&clks IMX6QDL_CLK_IPU2>,
 217                                  <&clks IMX6QDL_CLK_IPU2_DI0>,
 218                                  <&clks IMX6QDL_CLK_IPU2_DI1>;
 219                         clock-names = "bus", "di0", "di1";
 220                         resets = <&src 4>;
 221
 222                         ipu2_csi0: port@0 {
 223                                 reg = <0>;
 224
 225                                 ipu2_csi0_from_mipi_vc2: endpoint {
 226                                         remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
 227                                 };
 228                         };
 229
 230                         ipu2_csi1: port@1 {
 231                                 reg = <1>;
 232
 233                                 ipu2_csi1_from_ipu2_csi1_mux: endpoint {
 234                                         remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
 235                                 };
 236                         };
 237
 238                         ipu2_di0: port@2 {
 239                                 #address-cells = <1>;
 240                                 #size-cells = <0>;
 241                                 reg = <2>;
 242
 243                                 ipu2_di0_disp0: endpoint@0 {
 244                                         reg = <0>;
 245                                 };
 246
 247                                 ipu2_di0_hdmi: endpoint@1 {
 248                                         reg = <1>;
 249                                         remote-endpoint = <&hdmi_mux_2>;
 250                                 };
 251
 252                                 ipu2_di0_mipi: endpoint@2 {
 253                                         reg = <2>;
 254                                         remote-endpoint = <&mipi_mux_2>;
 255                                 };
 256
 257                                 ipu2_di0_lvds0: endpoint@3 {
 258                                         reg = <3>;
 259                                         remote-endpoint = <&lvds0_mux_2>;
 260                                 };
 261
 262                                 ipu2_di0_lvds1: endpoint@4 {
 263                                         reg = <4>;
 264                                         remote-endpoint = <&lvds1_mux_2>;
 265                                 };
 266                         };
 267
 268                         ipu2_di1: port@3 {
 269                                 #address-cells = <1>;
 270                                 #size-cells = <0>;
 271                                 reg = <3>;
 272
 273                                 ipu2_di1_hdmi: endpoint@1 {
 274                                         reg = <1>;
 275                                         remote-endpoint = <&hdmi_mux_3>;
 276                                 };
 277
 278                                 ipu2_di1_mipi: endpoint@2 {
 279                                         reg = <2>;
 280                                         remote-endpoint = <&mipi_mux_3>;
 281                                 };
 282
 283                                 ipu2_di1_lvds0: endpoint@3 {
 284                                         reg = <3>;
 285                                         remote-endpoint = <&lvds0_mux_3>;
 286                                 };
 287
 288                                 ipu2_di1_lvds1: endpoint@4 {
 289                                         reg = <4>;
 290                                         remote-endpoint = <&lvds1_mux_3>;
 291                                 };
 292                         };
 293                 };
 294         };
 295
 296         capture-subsystem {
 297                 compatible = "fsl,imx-capture-subsystem";
 298                 ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>;
 299         };
 300
 301         display-subsystem {
 302                 compatible = "fsl,imx-display-subsystem";
 303                 ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
 304         };
 305 };
 306
 307 &gpio1 {
 308         gpio-ranges = <&iomuxc  0 136  2>, <&iomuxc  2 141 1>, <&iomuxc  3 139 1>,
 309                       <&iomuxc  4 142  2>, <&iomuxc  6 140 1>, <&iomuxc  7 144 2>,
 310                       <&iomuxc  9 138  1>, <&iomuxc 10 213 3>, <&iomuxc 13  20 1>,
 311                       <&iomuxc 14  19  1>, <&iomuxc 15  21 1>, <&iomuxc 16 208 1>,
 312                       <&iomuxc 17 207  1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,
 313                       <&iomuxc 22 116 10>;
 314 };
 315
 316 &gpio2 {
 317         gpio-ranges = <&iomuxc  0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
 318                       <&iomuxc 31  44  1>;
 319 };
 320
 321 &gpio3 {
 322         gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
 323 };
 324
 325 &gpio4 {
 326         gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
 327 };
 328
 329 &gpio5 {
 330         gpio-ranges = <&iomuxc 0  85  1>, <&iomuxc  2  34  1>, <&iomuxc 4 53 1>,
 331                       <&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
 332 };
 333
 334 &gpio6 {
 335         gpio-ranges = <&iomuxc  0 164 6>, <&iomuxc  6  54 1>, <&iomuxc  7 181  5>,
 336                       <&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19  22 12>,
 337                       <&iomuxc 31  86 1>;
 338 };
 339
 340 &gpio7 {
 341         gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
 342 };
 343
 344 &gpr {
 345         ipu1_csi0_mux {
 346                 compatible = "video-mux";
 347                 mux-controls = <&mux 0>;
 348                 #address-cells = <1>;
 349                 #size-cells = <0>;
 350
 351                 port@0 {
 352                         reg = <0>;
 353
 354                         ipu1_csi0_mux_from_mipi_vc0: endpoint {
 355                                 remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
 356                         };
 357                 };
 358
 359                 port@1 {
 360                         reg = <1>;
 361
 362                         ipu1_csi0_mux_from_parallel_sensor: endpoint {
 363                         };
 364                 };
 365
 366                 port@2 {
 367                         reg = <2>;
 368
 369                         ipu1_csi0_mux_to_ipu1_csi0: endpoint {
 370                                 remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
 371                         };
 372                 };
 373         };
 374
 375         ipu2_csi1_mux {
 376                 compatible = "video-mux";
 377                 mux-controls = <&mux 1>;
 378                 #address-cells = <1>;
 379                 #size-cells = <0>;
 380
 381                 port@0 {
 382                         reg = <0>;
 383
 384                         ipu2_csi1_mux_from_mipi_vc3: endpoint {
 385                                 remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
 386                         };
 387                 };
 388
 389                 port@1 {
 390                         reg = <1>;
 391
 392                         ipu2_csi1_mux_from_parallel_sensor: endpoint {
 393                         };
 394                 };
 395
 396                 port@2 {
 397                         reg = <2>;
 398
 399                         ipu2_csi1_mux_to_ipu2_csi1: endpoint {
 400                                 remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
 401                         };
 402                 };
 403         };
 404 };
 405
 406 &hdmi {
 407         compatible = "fsl,imx6q-hdmi";
 408
 409         port@2 {
 410                 reg = <2>;
 411
 412                 hdmi_mux_2: endpoint {
 413                         remote-endpoint = <&ipu2_di0_hdmi>;
 414                 };
 415         };
 416
 417         port@3 {
 418                 reg = <3>;
 419
 420                 hdmi_mux_3: endpoint {
 421                         remote-endpoint = <&ipu2_di1_hdmi>;
 422                 };
 423         };
 424 };
 425
 426 &ipu1_csi1 {
 427         ipu1_csi1_from_mipi_vc1: endpoint {
 428                 remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
 429         };
 430 };
 431
 432 &ldb {
 433         clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
 434                  <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
 435                  <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
 436                  <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
 437         clock-names = "di0_pll", "di1_pll",
 438                       "di0_sel", "di1_sel", "di2_sel", "di3_sel",
 439                       "di0", "di1";
 440
 441         lvds-channel@0 {
 442                 port@2 {
 443                         reg = <2>;
 444
 445                         lvds0_mux_2: endpoint {
 446                                 remote-endpoint = <&ipu2_di0_lvds0>;
 447                         };
 448                 };
 449
 450                 port@3 {
 451                         reg = <3>;
 452
 453                         lvds0_mux_3: endpoint {
 454                                 remote-endpoint = <&ipu2_di1_lvds0>;
 455                         };
 456                 };
 457         };
 458
 459         lvds-channel@1 {
 460                 port@2 {
 461                         reg = <2>;
 462
 463                         lvds1_mux_2: endpoint {
 464                                 remote-endpoint = <&ipu2_di0_lvds1>;
 465                         };
 466                 };
 467
 468                 port@3 {
 469                         reg = <3>;
 470
 471                         lvds1_mux_3: endpoint {
 472                                 remote-endpoint = <&ipu2_di1_lvds1>;
 473                         };
 474                 };
 475         };
 476 };
 477
 478 &mipi_csi {
 479         port@1 {
 480                 reg = <1>;
 481
 482                 mipi_vc0_to_ipu1_csi0_mux: endpoint {
 483                         remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
 484                 };
 485         };
 486
 487         port@2 {
 488                 reg = <2>;
 489
 490                 mipi_vc1_to_ipu1_csi1: endpoint {
 491                         remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
 492                 };
 493         };
 494
 495         port@3 {
 496                 reg = <3>;
 497
 498                 mipi_vc2_to_ipu2_csi0: endpoint {
 499                         remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
 500                 };
 501         };
 502
 503         port@4 {
 504                 reg = <4>;
 505
 506                 mipi_vc3_to_ipu2_csi1_mux: endpoint {
 507                         remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
 508                 };
 509         };
 510 };
 511
 512 &mipi_dsi {
 513         ports {
 514                 port@2 {
 515                         reg = <2>;
 516
 517                         mipi_mux_2: endpoint {
 518                                 remote-endpoint = <&ipu2_di0_mipi>;
 519                         };
 520                 };
 521
 522                 port@3 {
 523                         reg = <3>;
 524
 525                         mipi_mux_3: endpoint {
 526                                 remote-endpoint = <&ipu2_di1_mipi>;
 527                         };
 528                 };
 529         };
 530 };
 531
 532 &mux {
 533         mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
 534                         <0x04 0x00100000>, /* MIPI_IPU2_MUX */
 535                         <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
 536                         <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
 537                         <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
 538                         <0x28 0x00000003>, /* DCIC1_MUX_CTL */
 539                         <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
 540 };
 541
 542 &vpu {
 543         compatible = "fsl,imx6q-vpu", "cnm,coda960";
 544 };