1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Copyright 2014-2019 Soeren Moch <smoch@web.de>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
12 model = "TBS2910 Matrix ARM mini PC";
13 compatible = "tbs,imx6q-tbs2910", "fsl,imx6q";
27 reg = <0x10000000 0x80000000>;
31 compatible = "gpio-fan";
32 pinctrl-names = "default";
33 pinctrl-0 = <&pinctrl_gpio_fan>;
34 gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
35 gpio-fan,speed-map = <0 0
40 compatible = "gpio-ir-receiver";
41 gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_ir>;
47 compatible = "gpio-leds";
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_gpio_leds>;
52 label = "blue_status_led";
53 gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
54 default-state = "keep";
58 reg_2p5v: regulator-2p5v {
59 compatible = "regulator-fixed";
60 regulator-name = "2P5V";
61 regulator-min-microvolt = <2500000>;
62 regulator-max-microvolt = <2500000>;
65 reg_3p3v: regulator-3p3v {
66 compatible = "regulator-fixed";
67 regulator-name = "3P3V";
68 regulator-min-microvolt = <3300000>;
69 regulator-max-microvolt = <3300000>;
72 reg_5p0v: regulator-5p0v {
73 compatible = "regulator-fixed";
74 regulator-name = "5P0V";
75 regulator-min-microvolt = <5000000>;
76 regulator-max-microvolt = <5000000>;
80 audio-codec = <&sgtl5000>;
83 "Mic Jack", "Mic Bias",
84 "Headphone Jack", "HP_OUT";
85 compatible = "fsl,imx-audio-sgtl5000";
86 model = "On-board Codec";
89 ssi-controller = <&ssi1>;
93 compatible = "fsl,imx-audio-spdif";
94 model = "On-board SPDIF";
95 spdif-controller = <&spdif>;
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_enet>;
108 phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
113 pinctrl-names = "default";
114 pinctrl-0 = <&pinctrl_hdmi>;
115 ddc-i2c-bus = <&i2c2>;
120 clock-frequency = <100000>;
121 pinctrl-names = "default";
122 pinctrl-0 = <&pinctrl_i2c1>;
125 sgtl5000: sgtl5000@a {
126 clocks = <&clks IMX6QDL_CLK_CKO>;
127 compatible = "fsl,sgtl5000";
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_sgtl5000>;
131 VDDA-supply = <®_2p5v>;
132 VDDIO-supply = <®_3p3v>;
137 clock-frequency = <100000>;
138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_i2c2>;
144 clock-frequency = <100000>;
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_i2c3>;
150 compatible = "dallas,ds1307";
156 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_pcie>;
158 reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
163 fsl,transmit-level-mV = <1104>;
164 fsl,transmit-boost-mdB = <3330>;
165 fsl,transmit-atten-16ths = <16>;
166 fsl,receive-eq-mdB = <3000>;
175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_spdif>;
185 pinctrl-names = "default";
186 pinctrl-0 = <&pinctrl_uart1>;
191 pinctrl-names = "default";
192 pinctrl-0 = <&pinctrl_uart2>;
197 vbus-supply = <®_5p0v>;
202 vbus-supply = <®_5p0v>;
203 pinctrl-names = "default";
204 pinctrl-0 = <&pinctrl_usbotg>;
205 disable-over-current;
210 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_usdhc2>;
213 cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
214 vmmc-supply = <®_3p3v>;
215 vqmmc-supply = <®_3p3v>;
216 voltage-ranges = <3300 3300>;
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_usdhc3>;
225 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
226 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
227 vmmc-supply = <®_3p3v>;
228 vqmmc-supply = <®_3p3v>;
229 voltage-ranges = <3300 3300>;
235 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_usdhc4>;
238 vmmc-supply = <®_3p3v>;
239 vqmmc-supply = <®_3p3v>;
240 voltage-ranges = <3300 3300>;
247 pinctrl_enet: enetgrp {
249 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
250 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
251 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
252 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
253 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
254 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
255 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
256 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
257 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
258 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
259 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
260 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
261 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
262 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
263 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
264 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
265 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b059
269 pinctrl_gpio_fan: gpiofangrp {
271 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x130b1
275 pinctrl_gpio_leds: gpioledsgrp {
277 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b1
281 pinctrl_hdmi: hdmigrp {
283 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
287 pinctrl_i2c1: i2c1grp {
289 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
290 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
294 pinctrl_i2c2: i2c2grp {
296 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
297 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
301 pinctrl_i2c3: i2c3grp {
303 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
304 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
310 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x17059
314 pinctrl_pcie: pciegrp {
316 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x17059
320 pinctrl_sgtl5000: sgtl5000grp {
322 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
323 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
324 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
325 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
326 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
330 pinctrl_spdif: spdifgrp {
331 fsl,pins = <MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091
335 pinctrl_uart1: uart1grp {
337 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
338 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
342 pinctrl_uart2: uart2grp {
344 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
345 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
349 pinctrl_usbotg: usbotggrp {
351 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
355 pinctrl_usdhc2: usdhc2grp {
357 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
358 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
359 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
360 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
361 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
362 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
363 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x17059
367 pinctrl_usdhc3: usdhc3grp {
369 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
370 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
371 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
372 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
373 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
374 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
375 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x17059
376 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x17059
380 pinctrl_usdhc4: usdhc4grp {
382 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
383 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
384 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
385 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
386 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
387 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
388 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
389 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
390 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
391 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059