arch/arm/dts/imx6q-mccmon6.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2019
   4  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+ or X11
   7  */
   8
   9 /dts-v1/;
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include "imx6q.dtsi"
  12
  13 / {
  14         model = "Liebherr Nenzig (LWN) iMX6Q";
  15         compatible = "lwn,imx6-mccmon6", "fsl,imx6";
  16
  17         aliases {
  18                 mmc0 = &usdhc3;
  19                 mmc1 = &usdhc2;
  20                 spi0 = &ecspi3;
  21         };
  22
  23         chosen {
  24                 stdout-path = &uart1;
  25         };
  26
  27         memory@10000000 {
  28                 reg = <0x10000000 0x80000000>;
  29         };
  30 };
  31
  32 &ecspi3 {
  33         cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
  34         pinctrl-names = "default";
  35         pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs &pinctrl_ecspi3_flwp>;
  36         spi-max-frequency = <25000000>;
  37         status = "okay";
  38
  39         s25sl032p: flash@0 {
  40                 #address-cells = <1>;
  41                 #size-cells = <1>;
  42                 compatible = "jedec,spi-nor";
  43                 spi-max-frequency = <40000000>;
  44                 reg = <0>;
  45         };
  46 };
  47
  48 &fec {
  49         pinctrl-names = "default";
  50         pinctrl-0 = <&pinctrl_enet>;
  51         phy-mode = "rgmii";
  52         phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
  53         phy-reset-duration = <10>;
  54         phy-reset-post-delay = <1>;
  55         /* KSZ9031 PHY SKEW setup - old values * 60 ps */
  56         rxc-skew-ps = <1860>;
  57         txc-skew-ps = <1860>;
  58         txen-skew-ps = <900>;
  59         rxdv-skew-ps = <900>;
  60         rxd0-skew-ps = <180>;
  61         rxd1-skew-ps = <180>;
  62         rxd2-skew-ps = <180>;
  63         rxd3-skew-ps = <180>;
  64         txd0-skew-ps = <120>;
  65         txd1-skew-ps = <300>;
  66         txd2-skew-ps = <0>;
  67         txd3-skew-ps = <120>;
  68         status = "okay";
  69 };
  70
  71 &i2c1 {
  72         clock-frequency = <100000>;
  73         pinctrl-names = "default";
  74         pinctrl-0 = <&pinctrl_i2c1>;
  75         status = "okay";
  76 };
  77
  78 &i2c2 {
  79         clock-frequency = <100000>;
  80         pinctrl-names = "default";
  81         pinctrl-0 = <&pinctrl_i2c2>;
  82         status = "okay";
  83
  84         pfuze100: pmic@8 {
  85                 compatible = "fsl,pfuze100";
  86                 reg = <0x08>;
  87
  88                 regulators {
  89                         sw1a_reg: sw1ab {
  90                                 regulator-min-microvolt = <300000>;
  91                                 regulator-max-microvolt = <1875000>;
  92                                 regulator-boot-on;
  93                                 regulator-always-on;
  94                                 regulator-ramp-delay = <6250>;
  95                         };
  96
  97                         sw1c_reg: sw1c {
  98                                 regulator-min-microvolt = <300000>;
  99                                 regulator-max-microvolt = <1875000>;
 100                                 regulator-boot-on;
 101                                 regulator-always-on;
 102                                 regulator-ramp-delay = <6250>;
 103                         };
 104
 105                         sw2_reg: sw2 {
 106                                 regulator-min-microvolt = <800000>;
 107                                 regulator-max-microvolt = <3950000>;
 108                                 regulator-boot-on;
 109                                 regulator-always-on;
 110                         };
 111
 112                         sw3a_reg: sw3a {
 113                                 regulator-min-microvolt = <400000>;
 114                                 regulator-max-microvolt = <1975000>;
 115                                 regulator-boot-on;
 116                                 regulator-always-on;
 117                         };
 118
 119                         sw3b_reg: sw3b {
 120                                 regulator-min-microvolt = <400000>;
 121                                 regulator-max-microvolt = <1975000>;
 122                                 regulator-boot-on;
 123                                 regulator-always-on;
 124                         };
 125
 126                         sw4_reg: sw4 {
 127                                 regulator-min-microvolt = <800000>;
 128                                 regulator-max-microvolt = <3300000>;
 129                         };
 130
 131                         swbst_reg: swbst {
 132                                 regulator-min-microvolt = <5000000>;
 133                                 regulator-max-microvolt = <5150000>;
 134                         };
 135
 136                         snvs_reg: vsnvs {
 137                                 regulator-min-microvolt = <1000000>;
 138                                 regulator-max-microvolt = <3000000>;
 139                                 regulator-boot-on;
 140                                 regulator-always-on;
 141                         };
 142
 143                         vref_reg: vrefddr {
 144                                 regulator-boot-on;
 145                                 regulator-always-on;
 146                         };
 147
 148                         vgen1_reg: vgen1 {
 149                                 regulator-min-microvolt = <800000>;
 150                                 regulator-max-microvolt = <1550000>;
 151                         };
 152
 153                         vgen2_reg: vgen2 {
 154                                 regulator-min-microvolt = <800000>;
 155                                 regulator-max-microvolt = <1550000>;
 156                         };
 157
 158                         vgen3_reg: vgen3 {
 159                                 regulator-min-microvolt = <1800000>;
 160                                 regulator-max-microvolt = <3300000>;
 161                         };
 162
 163                         vgen4_reg: vgen4 {
 164                                 regulator-min-microvolt = <1800000>;
 165                                 regulator-max-microvolt = <3300000>;
 166                                 regulator-always-on;
 167                         };
 168
 169                         vgen5_reg: vgen5 {
 170                                 regulator-min-microvolt = <1800000>;
 171                                 regulator-max-microvolt = <3300000>;
 172                                 regulator-always-on;
 173                         };
 174
 175                         vgen6_reg: vgen6 {
 176                                 regulator-min-microvolt = <1800000>;
 177                                 regulator-max-microvolt = <3300000>;
 178                                 regulator-always-on;
 179                         };
 180                 };
 181         };
 182 };
 183
 184 &weim {
 185         pinctrl-names = "default";
 186         pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
 187         ranges = <0 0 0x08000000 0x08000000>;
 188         status = "okay";
 189
 190         nor@0,0 {
 191                 compatible = "cfi-flash";
 192                 reg = <0 0 0x02000000>;
 193                 #address-cells = <1>;
 194                 #size-cells = <1>;
 195                 bank-width = <2>;
 196                 use-advanced-sector-protection;
 197                 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
 198                                 0x0000c000 0x1404a38e 0x00000000>;
 199         };
 200 };
 201
 202 &iomuxc {
 203         pinctrl-names = "default";
 204         pinctrl-0 = <&pinctrl_hog>;
 205
 206         pinctrl_ecspi3: ecspi3grp {
 207                 fsl,pins = <
 208                         MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO      0x100b1
 209                         MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI      0x100b1
 210                         MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK      0x100b1
 211                 >;
 212         };
 213
 214         pinctrl_ecspi3_cs: ecspi3csgrp {
 215                 fsl,pins = <
 216                         MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000
 217                 >;
 218         };
 219
 220         pinctrl_ecspi3_flwp: ecspi3flwpgrp {
 221                 fsl,pins = <
 222                         MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x80000000
 223                 >;
 224         };
 225
 226         pinctrl_enet: enetgrp {
 227                 fsl,pins = <
 228                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 229                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 230                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
 231                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
 232                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
 233                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
 234                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
 235                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
 236                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 237                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
 238                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
 239                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
 240                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
 241                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
 242                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
 243                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
 244                         MX6QDL_PAD_GPIO_6__ENET_IRQ             0x000b1
 245                         MX6QDL_PAD_ENET_RXD0__GPIO1_IO27        0x1b0b0
 246                 >;
 247         };
 248
 249         pinctrl_hog: hoggrp {
 250                 fsl,pins = <
 251                         MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
 252                         MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0
 253                 >;
 254         };
 255
 256         pinctrl_i2c1: i2c1grp {
 257                 fsl,pins = <
 258                         MX6QDL_PAD_CSI0_DAT9__I2C1_SCL  0x4001b8b1
 259                         MX6QDL_PAD_CSI0_DAT8__I2C1_SDA  0x4001b8b1
 260                 >;
 261         };
 262
 263         pinctrl_i2c2: i2c2grp {
 264                 fsl,pins = <
 265                         MX6QDL_PAD_KEY_COL3__I2C2_SCL   0x4001b8b1
 266                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA   0x4001b8b1
 267                 >;
 268         };
 269
 270         pinctrl_uart1: uart1grp {
 271                 fsl,pins = <
 272                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
 273                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
 274                 >;
 275         };
 276
 277         pinctrl_usdhc2: usdhc2grp {
 278                 fsl,pins = <
 279                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
 280                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
 281                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
 282                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
 283                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
 284                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
 285                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x1b0b1
 286                 >;
 287         };
 288
 289         pinctrl_usdhc3: usdhc3grp {
 290                 fsl,pins = <
 291                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 292                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 293                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 294                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 295                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 296                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 297                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
 298                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
 299                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
 300                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
 301                         MX6QDL_PAD_SD3_RST__SD3_RESET           0x17059
 302                 >;
 303         };
 304
 305         pinctrl_weim_cs0: weimcs0grp {
 306                 fsl,pins = <
 307                         MX6QDL_PAD_EIM_CS0__EIM_CS0_B           0xb0b1
 308                 >;
 309         };
 310
 311         pinctrl_weim_nor: weimnorgrp {
 312                 fsl,pins = <
 313                         MX6QDL_PAD_EIM_OE__EIM_OE_B             0xb0b1
 314                         MX6QDL_PAD_EIM_RW__EIM_RW               0xb0b1
 315                         MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
 316                         MX6QDL_PAD_EIM_D16__EIM_DATA16          0x1b0b0
 317                         MX6QDL_PAD_EIM_D17__EIM_DATA17          0x1b0b0
 318                         MX6QDL_PAD_EIM_D18__EIM_DATA18          0x1b0b0
 319                         MX6QDL_PAD_EIM_D19__EIM_DATA19          0x1b0b0
 320                         MX6QDL_PAD_EIM_D20__EIM_DATA20          0x1b0b0
 321                         MX6QDL_PAD_EIM_D21__EIM_DATA21          0x1b0b0
 322                         MX6QDL_PAD_EIM_D22__EIM_DATA22          0x1b0b0
 323                         MX6QDL_PAD_EIM_D23__EIM_DATA23          0x1b0b0
 324                         MX6QDL_PAD_EIM_D24__EIM_DATA24          0x1b0b0
 325                         MX6QDL_PAD_EIM_D25__EIM_DATA25          0x1b0b0
 326                         MX6QDL_PAD_EIM_D26__EIM_DATA26          0x1b0b0
 327                         MX6QDL_PAD_EIM_D27__EIM_DATA27          0x1b0b0
 328                         MX6QDL_PAD_EIM_D28__EIM_DATA28          0x1b0b0
 329                         MX6QDL_PAD_EIM_D29__EIM_DATA29          0x1b0b0
 330                         MX6QDL_PAD_EIM_D30__EIM_DATA30          0x1b0b0
 331                         MX6QDL_PAD_EIM_D31__EIM_DATA31          0x1b0b0
 332                         MX6QDL_PAD_EIM_A23__EIM_ADDR23          0xb0b1
 333                         MX6QDL_PAD_EIM_A22__EIM_ADDR22          0xb0b1
 334                         MX6QDL_PAD_EIM_A21__EIM_ADDR21          0xb0b1
 335                         MX6QDL_PAD_EIM_A20__EIM_ADDR20          0xb0b1
 336                         MX6QDL_PAD_EIM_A19__EIM_ADDR19          0xb0b1
 337                         MX6QDL_PAD_EIM_A18__EIM_ADDR18          0xb0b1
 338                         MX6QDL_PAD_EIM_A17__EIM_ADDR17          0xb0b1
 339                         MX6QDL_PAD_EIM_A16__EIM_ADDR16          0xb0b1
 340                         MX6QDL_PAD_EIM_DA15__EIM_AD15           0xb0b1
 341                         MX6QDL_PAD_EIM_DA14__EIM_AD14           0xb0b1
 342                         MX6QDL_PAD_EIM_DA13__EIM_AD13           0xb0b1
 343                         MX6QDL_PAD_EIM_DA12__EIM_AD12           0xb0b1
 344                         MX6QDL_PAD_EIM_DA11__EIM_AD11           0xb0b1
 345                         MX6QDL_PAD_EIM_DA10__EIM_AD10           0xb0b1
 346                         MX6QDL_PAD_EIM_DA9__EIM_AD09            0xb0b1
 347                         MX6QDL_PAD_EIM_DA8__EIM_AD08            0xb0b1
 348                         MX6QDL_PAD_EIM_DA7__EIM_AD07            0xb0b1
 349                         MX6QDL_PAD_EIM_DA6__EIM_AD06            0xb0b1
 350                         MX6QDL_PAD_EIM_DA5__EIM_AD05            0xb0b1
 351                         MX6QDL_PAD_EIM_DA4__EIM_AD04            0xb0b1
 352                         MX6QDL_PAD_EIM_DA3__EIM_AD03            0xb0b1
 353                         MX6QDL_PAD_EIM_DA2__EIM_AD02            0xb0b1
 354                         MX6QDL_PAD_EIM_DA1__EIM_AD01            0xb0b1
 355                         MX6QDL_PAD_EIM_DA0__EIM_AD00            0xb0b1
 356                 >;
 357         };
 358 };
 359
 360 &uart1 {
 361         pinctrl-names = "default";
 362         pinctrl-0 = <&pinctrl_uart1>;
 363         status = "okay";
 364 };
 365
 366 &usdhc2 {
 367         pinctrl-names = "default";
 368         pinctrl-0 = <&pinctrl_usdhc2>;
 369         bus-width = <4>;
 370         cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
 371         status = "okay";
 372 };
 373
 374 &usdhc3 {
 375         pinctrl-names = "default";
 376         pinctrl-0 = <&pinctrl_usdhc3>;
 377         bus-width = <8>;
 378         non-removable;
 379         no-1-8-v;
 380         keep-power-in-suspend;
 381         status = "okay";
 382 };