3 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
13 #include <dt-bindings/gpio/gpio.h>
17 model = "Liebherr (LWN) display5 i.MX6 Quad Board";
18 compatible = "lwn,display5", "fsl,imx6q";
21 device_type = "memory";
22 reg = <0x10000000 0x40000000>;
27 cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs &pinctrl_ecspi2_flwp>;
35 compatible = "jedec,spi-nor";
36 spi-max-frequency = <40000000>;
45 label = "u-boot (spi)";
46 reg = <0x20000 0x100000>;
50 label = "uboot-env (spi)";
51 reg = <0x120000 0x10000>;
54 label = "uboot-envr (spi)";
55 reg = <0x130000 0x10000>;
58 label = "linux-recovery (spi)";
59 reg = <0x140000 0x800000>;
62 label = "swupdate-fitImg (spi)";
63 reg = <0x940000 0x400000>;
66 label = "swupdate-initramfs (spi)";
67 reg = <0xD40000 0x800000>;
73 cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
74 pinctrl-names = "default";
75 pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs &pinctrl_ecspi3_flwp>;
80 pinctrl-names = "default";
81 pinctrl-0 = <&pinctrl_enet>;
82 phy-handle = <ðernet_phy0>;
83 phy-mode = "rgmii-id";
89 ethernet_phy0: ethernet-phy@0 {
90 compatible = "marvell,88E1510";
91 device_type = "ethernet-phy";
92 /* Set LED0 control: */
93 /* On - Link, Blink - Activity, Off - No Link */
94 marvell,reg-init = <3 0x10 0 0x1011>;
102 clock-frequency = <400000>;
103 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_i2c1>;
108 #sound-dai-cells = <0>;
109 compatible = "nxp,tfa9879";
115 clock-frequency = <400000>;
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_i2c2>;
122 clock-frequency = <400000>;
123 pinctrl-names = "default";
124 pinctrl-0 = <&pinctrl_i2c3>;
128 compatible = "atmel,24c256";
134 compatible = "fsl,pfuze100";
139 regulator-min-microvolt = <300000>;
140 regulator-max-microvolt = <1875000>;
143 regulator-ramp-delay = <6250>;
147 regulator-min-microvolt = <300000>;
148 regulator-max-microvolt = <1875000>;
151 regulator-ramp-delay = <6250>;
155 regulator-min-microvolt = <800000>;
156 regulator-max-microvolt = <3950000>;
162 regulator-min-microvolt = <400000>;
163 regulator-max-microvolt = <1975000>;
169 regulator-min-microvolt = <400000>;
170 regulator-max-microvolt = <1975000>;
176 regulator-min-microvolt = <800000>;
177 regulator-max-microvolt = <3300000>;
181 regulator-min-microvolt = <5000000>;
182 regulator-max-microvolt = <5150000>;
186 regulator-min-microvolt = <1000000>;
187 regulator-max-microvolt = <3000000>;
198 regulator-min-microvolt = <800000>;
199 regulator-max-microvolt = <1550000>;
203 regulator-min-microvolt = <800000>;
204 regulator-max-microvolt = <1550000>;
208 regulator-min-microvolt = <1800000>;
209 regulator-max-microvolt = <3300000>;
213 regulator-min-microvolt = <1800000>;
214 regulator-max-microvolt = <3300000>;
219 regulator-min-microvolt = <1800000>;
220 regulator-max-microvolt = <3300000>;
225 regulator-min-microvolt = <1800000>;
226 regulator-max-microvolt = <3300000>;
234 pinctrl-names = "default";
235 pinctrl-0 = <&pinctrl_uart4>;
241 pinctrl-names = "default";
242 pinctrl-0 = <&pinctrl_uart5>;
247 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_usdhc4>;
255 pinctrl_ecspi2: ecspi2grp {
257 MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1
258 MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1
259 MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1
263 pinctrl_ecspi2_cs: ecspi2csgrp {
265 MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1
269 pinctrl_ecspi2_flwp: ecspi2flwpgrp {
271 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
275 pinctrl_ecspi3: ecspi3grp {
277 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
278 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
279 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
283 pinctrl_ecspi3_cs: ecspi3csgrp {
285 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b0
289 pinctrl_ecspi3_flwp: ecspi3flwpgrp {
291 MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0
295 pinctrl_enet: enetgrp {
297 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
298 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
299 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
300 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
301 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
302 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
303 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
304 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
305 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
306 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
307 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
308 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
309 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
310 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
311 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
312 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
313 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
314 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0
318 pinctrl_i2c1: i2c1grp {
320 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
321 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
325 pinctrl_i2c2: i2c2grp {
327 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
328 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
332 pinctrl_i2c3: i2c3grp {
334 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
335 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
339 pinctrl_uart4: uart4grp {
341 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
342 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
343 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
344 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
348 pinctrl_uart5: uart5grp {
350 MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
351 MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
355 pinctrl_usdhc4: usdhc4grp {
357 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
358 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
359 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
360 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
361 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
362 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
363 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
364 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
365 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
366 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
367 MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x17059