arch/arm/dts/imx6q-cm-fx6.dts

   1 /*
   2  * Copyright 2013 CompuLab Ltd.
   3  *
   4  * Author: Valentin Raevsky <valentin@compulab.co.il>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /dts-v1/;
  15 #include "imx6q.dtsi"
  16
  17 / {
  18         model = "CompuLab CM-FX6";
  19         compatible = "compulab,cm-fx6", "fsl,imx6q";
  20
  21         memory {
  22                 reg = <0x10000000 0x80000000>;
  23         };
  24
  25         leds {
  26                 compatible = "gpio-leds";
  27
  28                 heartbeat-led {
  29                         label = "Heartbeat";
  30                         gpios = <&gpio2 31 0>;
  31                         linux,default-trigger = "heartbeat";
  32                 };
  33         };
  34 };
  35
  36 &fec {
  37         pinctrl-names = "default";
  38         pinctrl-0 = <&pinctrl_enet>;
  39         phy-mode = "rgmii";
  40         status = "okay";
  41 };
  42
  43 &gpmi {
  44         pinctrl-names = "default";
  45         pinctrl-0 = <&pinctrl_gpmi_nand>;
  46         status = "okay";
  47 };
  48
  49 &iomuxc {
  50         imx6q-cm-fx6 {
  51                 pinctrl_enet: enetgrp {
  52                         fsl,pins = <
  53                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
  54                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
  55                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
  56                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
  57                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
  58                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
  59                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
  60                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
  61                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
  62                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
  63                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
  64                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
  65                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
  66                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
  67                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
  68                                 MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
  69                         >;
  70                 };
  71
  72                 pinctrl_gpmi_nand: gpminandgrp {
  73                         fsl,pins = <
  74                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
  75                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
  76                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
  77                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
  78                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
  79                                 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
  80                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
  81                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
  82                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
  83                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
  84                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
  85                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
  86                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
  87                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
  88                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
  89                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
  90                                 MX6QDL_PAD_SD4_DAT0__NAND_DQS           0x00b1
  91                         >;
  92                 };
  93
  94                 pinctrl_uart4: uart4grp {
  95                         fsl,pins = <
  96                                 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
  97                                 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
  98                         >;
  99                 };
 100         };
 101 };
 102
 103 &uart4 {
 104         pinctrl-names = "default";
 105         pinctrl-0 = <&pinctrl_uart4>;
 106         status = "okay";
 107 };
 108
 109 &sata {
 110         status = "okay";
 111 };
 112
 113 &usdhc3 {
 114         status = "okay";
 115 };