arch/arm/dts/imx6q-cm-fx6.dts

   1 /*
   2  * Copyright 2013 CompuLab Ltd.
   3  *
   4  * Author: Valentin Raevsky <valentin@compulab.co.il>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License
  13  *     version 2 as published by the Free Software Foundation.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 /dts-v1/;
  45 #include <dt-bindings/gpio/gpio.h>
  46 #include "imx6q.dtsi"
  47
  48 / {
  49         model = "CompuLab CM-FX6";
  50         compatible = "compulab,cm-fx6", "fsl,imx6q";
  51
  52         memory {
  53                 reg = <0x10000000 0x80000000>;
  54         };
  55
  56         leds {
  57                 compatible = "gpio-leds";
  58
  59                 heartbeat-led {
  60                         label = "Heartbeat";
  61                         gpios = <&gpio2 31 0>;
  62                         linux,default-trigger = "heartbeat";
  63                 };
  64         };
  65
  66         awnh387_pwrseq: pwrseq {
  67                 pinctrl-names = "default";
  68                 pinctrl-0 = <&pinctrl_pwrseq>;
  69                 compatible = "mmc-pwrseq-sd8787";
  70                 powerdown-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>;
  71                 reset-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
  72         };
  73
  74         reg_pcie_power_on_gpio: regulator-pcie-power-on-gpio {
  75                 compatible = "regulator-fixed";
  76                 regulator-name = "regulator-pcie-power-on-gpio";
  77                 regulator-min-microvolt = <3300000>;
  78                 regulator-max-microvolt = <3300000>;
  79                 gpio = <&gpio2 24 GPIO_ACTIVE_LOW>;
  80         };
  81
  82         reg_usb_h1_vbus: usb_h1_vbus {
  83                 compatible = "regulator-fixed";
  84                 regulator-name = "usb_h1_vbus";
  85                 regulator-min-microvolt = <5000000>;
  86                 regulator-max-microvolt = <5000000>;
  87                 gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
  88                 enable-active-high;
  89         };
  90
  91         reg_usb_otg_vbus: usb_otg_vbus {
  92                 compatible = "regulator-fixed";
  93                 regulator-name = "usb_otg_vbus";
  94                 regulator-min-microvolt = <5000000>;
  95                 regulator-max-microvolt = <5000000>;
  96                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  97                 enable-active-high;
  98         };
  99
 100         sound-analog {
 101                 compatible = "simple-audio-card";
 102                 simple-audio-card,name = "On-board analog audio";
 103                 simple-audio-card,widgets =
 104                         "Headphone", "Headphone Jack",
 105                         "Line", "Line Out",
 106                         "Microphone", "Mic Jack",
 107                         "Line", "Line In";
 108                 simple-audio-card,routing =
 109                         "Headphone Jack", "RHPOUT",
 110                         "Headphone Jack", "LHPOUT",
 111                         "MICIN", "Mic Bias",
 112                         "Mic Bias", "Mic Jack";
 113                 simple-audio-card,format = "i2s";
 114                 simple-audio-card,bitclock-master = <&sound_master>;
 115                 simple-audio-card,frame-master = <&sound_master>;
 116                 simple-audio-card,bitclock-inversion;
 117
 118                 sound_master: simple-audio-card,cpu {
 119                         sound-dai = <&ssi2>;
 120                         system-clock-frequency = <2822400>;
 121                 };
 122
 123                 simple-audio-card,codec {
 124                         sound-dai = <&wm8731>;
 125                 };
 126         };
 127
 128         sound-spdif {
 129                 compatible = "fsl,imx-audio-spdif";
 130                 model = "imx-spdif";
 131                 spdif-controller = <&spdif>;
 132                 spdif-out;
 133                 spdif-in;
 134         };
 135 };
 136
 137 /*
 138  * The U-Boot: audio mux node has been removed because the required dt-bindings
 139  * header file is not present in the U-Boot.
 140  */
 141
 142 &cpu0 {
 143         /*
 144          * Although the imx6q fuse indicates that 1.2GHz operation is possible,
 145          * the module behaves unstable at this frequency. Hence, remove the
 146          * 1.2GHz operation point here.
 147          */
 148         operating-points = <
 149                 /* kHz  uV */
 150                 996000  1250000
 151                 852000  1250000
 152                 792000  1175000
 153                 396000  975000
 154         >;
 155         fsl,soc-operating-points = <
 156                 /* ARM kHz      SOC-PU uV */
 157                 996000          1250000
 158                 852000          1250000
 159                 792000          1175000
 160                 396000          1175000
 161         >;
 162 };
 163
 164 &ecspi1 {
 165         cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>, <&gpio3 19 GPIO_ACTIVE_HIGH>;
 166         pinctrl-names = "default";
 167         pinctrl-0 = <&pinctrl_ecspi1>;
 168         status = "okay";
 169
 170         m25p80@0 {
 171                 #address-cells = <1>;
 172                 #size-cells = <1>;
 173                 compatible = "st,m25p", "jedec,spi-nor";
 174                 spi-max-frequency = <20000000>;
 175                 reg = <0>;
 176         };
 177 };
 178
 179 &fec {
 180         pinctrl-names = "default";
 181         pinctrl-0 = <&pinctrl_enet>;
 182         phy-mode = "rgmii";
 183         status = "okay";
 184 };
 185
 186 &gpmi {
 187         pinctrl-names = "default";
 188         pinctrl-0 = <&pinctrl_gpmi_nand>;
 189         status = "okay";
 190 };
 191
 192 &i2c3 {
 193         pinctrl-names = "default";
 194         pinctrl-0 = <&pinctrl_i2c3>;
 195         status = "okay";
 196         clock-frequency = <100000>;
 197
 198         eeprom@50 {
 199                 compatible = "atmel,24c02";
 200                 reg = <0x50>;
 201                 pagesize = <16>;
 202         };
 203
 204         wm8731: codec@1a {
 205                 #sound-dai-cells = <0>;
 206                 compatible = "wlf,wm8731";
 207                 reg = <0x1a>;
 208         };
 209 };
 210
 211 &iomuxc {
 212         pinctrl_audmux: audmuxgrp {
 213                 fsl,pins = <
 214                         MX6QDL_PAD_SD2_CMD__AUD4_RXC   0x17059
 215                         MX6QDL_PAD_SD2_DAT0__AUD4_RXD  0x17059
 216                         MX6QDL_PAD_SD2_DAT3__AUD4_TXC  0x17059
 217                         MX6QDL_PAD_SD2_DAT2__AUD4_TXD  0x17059
 218                         MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x17059
 219                 >;
 220         };
 221
 222         pinctrl_ecspi1: ecspi1grp {
 223                 fsl,pins = <
 224                         MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
 225                         MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
 226                         MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
 227                         MX6QDL_PAD_EIM_EB2__GPIO2_IO30  0x100b1
 228                         MX6QDL_PAD_EIM_D19__GPIO3_IO19  0x100b1
 229                 >;
 230         };
 231
 232         pinctrl_enet: enetgrp {
 233                 fsl,pins = <
 234                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 235                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 236                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 237                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 238                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 239                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 240                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 241                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 242                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 243                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 244                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 245                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 246                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 247                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 248                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 249                 >;
 250         };
 251
 252         pinctrl_gpmi_nand: gpminandgrp {
 253                 fsl,pins = <
 254                         MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 255                         MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 256                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 257                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 258                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 259                         MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
 260                         MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 261                         MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 262                         MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 263                         MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 264                         MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 265                         MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 266                         MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 267                         MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 268                         MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 269                         MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 270                         MX6QDL_PAD_SD4_DAT0__NAND_DQS           0x00b1
 271                 >;
 272         };
 273
 274         pinctrl_i2c3: i2c3grp {
 275                 fsl,pins = <
 276                         MX6QDL_PAD_GPIO_3__I2C3_SCL     0x4001b8b1
 277                         MX6QDL_PAD_GPIO_6__I2C3_SDA     0x4001b8b1
 278                 >;
 279         };
 280
 281         pinctrl_pcie: pciegrp {
 282                 fsl,pins = <
 283                         MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b1
 284                         MX6QDL_PAD_EIM_CS1__GPIO2_IO24  0x1b0b1
 285                 >;
 286         };
 287
 288         pinctrl_pwrseq: pwrseqgrp {
 289                 fsl,pins = <
 290                         MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x1b0b0
 291                         MX6QDL_PAD_NANDF_CS3__GPIO6_IO16        0x1b0b0
 292                 >;
 293         };
 294
 295         pinctrl_spdif: spdifgrp {
 296                 fsl,pins = <
 297                         MX6QDL_PAD_GPIO_16__SPDIF_IN  0x1b0b0
 298                         MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0
 299                 >;
 300         };
 301
 302         pinctrl_uart4: uart4grp {
 303                 fsl,pins = <
 304                         MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
 305                         MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
 306                 >;
 307         };
 308
 309         pinctrl_usbh1: usbh1grp {
 310                 fsl,pins = <
 311                         MX6QDL_PAD_SD3_RST__GPIO7_IO08  0x1b0b1
 312                 >;
 313         };
 314
 315         pinctrl_usbotg: usbotggrp {
 316                 fsl,pins = <
 317                         MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID       0x17059
 318                         MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x130b0
 319                 >;
 320         };
 321
 322         pinctrl_usdhc1: usdhc1grp {
 323                 fsl,pins = <
 324                         MX6QDL_PAD_SD1_CMD__SD1_CMD     0x17071
 325                         MX6QDL_PAD_SD1_CLK__SD1_CLK     0x10071
 326                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0  0x17071
 327                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1  0x17071
 328                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2  0x17071
 329                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3  0x17071
 330                 >;
 331         };
 332 };
 333
 334 &pcie {
 335         pinctrl-names = "default";
 336         pinctrl-0 = <&pinctrl_pcie>;
 337         reset-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;
 338         vpcie-supply = <&reg_pcie_power_on_gpio>;
 339         status = "okay";
 340 };
 341
 342 &sata {
 343         status = "okay";
 344 };
 345
 346 &snvs_poweroff {
 347         status = "okay";
 348 };
 349
 350 &spdif {
 351         pinctrl-names = "default";
 352         pinctrl-0 = <&pinctrl_spdif>;
 353         status = "okay";
 354 };
 355
 356 &ssi2 {
 357         assigned-clocks = <&clks IMX6QDL_CLK_SSI2_SEL>,
 358                         <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
 359         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
 360         assigned-clock-rates = <0>, <786432000>;
 361         status = "okay";
 362 };
 363
 364 &uart4 {
 365         pinctrl-names = "default";
 366         pinctrl-0 = <&pinctrl_uart4>;
 367         status = "okay";
 368 };
 369
 370 &usbh1 {
 371         vbus-supply = <&reg_usb_h1_vbus>;
 372         pinctrl-names = "default";
 373         pinctrl-0 = <&pinctrl_usbh1>;
 374         status = "okay";
 375 };
 376
 377 &usbotg {
 378         vbus-supply = <&reg_usb_otg_vbus>;
 379         pinctrl-names = "default";
 380         pinctrl-0 = <&pinctrl_usbotg>;
 381         dr_mode = "otg";
 382         status = "okay";
 383 };
 384
 385 &usdhc1 {
 386         pinctrl-names = "default";
 387         pinctrl-0 = <&pinctrl_usdhc1>;
 388         mmc-pwrseq = <&awnh387_pwrseq>;
 389         non-removable;
 390         /*
 391          * If the OS probes the Bluetooth AMP function advertised on this bus
 392          * but the firmware in place does not support it, the WiFi/BT module
 393          * gets unresponsive.
 394          * Users who configured their OS properly can enable this node to gain
 395          * WiFi and/or plain Bluetooth support.
 396          */
 397         status = "disabled";
 398 };
 399
 400 /* The U-Boot: enable usdhc3 for mmc boot */
 401 &usdhc3 {
 402         status = "okay";
 403 };