2 * Copyright 2018 Logic PD
3 * This file is adapted from imx6qdl-sabresd.dtsi.
4 * Copyright 2012 Freescale Semiconductor, Inc.
5 * Copyright 2011 Linaro Ltd.
7 * The code contained herein is licensed under the GNU General Public
8 * License. You may obtain a copy of the GNU General Public License
9 * Version 2 or later at the following locations:
11 * http://www.opensource.org/licenses/gpl-license.html
12 * http://www.gnu.org/copyleft/gpl.html
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
24 reg = <0x10000000 0x80000000>;
27 reg_wl18xx_vmmc: regulator-wl18xx {
28 compatible = "regulator-fixed";
29 regulator-name = "vwl1837";
30 regulator-min-microvolt = <3300000>;
31 regulator-max-microvolt = <3300000>;
32 gpio = <&gpio7 0 GPIO_ACTIVE_HIGH>;
33 startup-delay-us = <70000>;
38 /* Reroute power feeding the CPU to come from the external PMIC */
41 vin-supply = <&sw1a_reg>;
46 vin-supply = <&sw1c_reg>;
50 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
51 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
52 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
53 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_gpmi_nand>;
64 clock-frequency = <100000>;
65 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_i2c3>;
70 compatible = "fsl,pfuze100";
75 regulator-min-microvolt = <725000>;
76 regulator-max-microvolt = <1450000>;
77 regulator-name = "vddcore";
80 regulator-ramp-delay = <6250>;
84 regulator-min-microvolt = <725000>;
85 regulator-max-microvolt = <1450000>;
86 regulator-name = "vddsoc";
89 regulator-ramp-delay = <6250>;
93 regulator-min-microvolt = <3300000>;
94 regulator-max-microvolt = <3300000>;
95 regulator-name = "gen_3v3";
97 /* regulator-always-on; */
101 regulator-min-microvolt = <400000>;
102 regulator-max-microvolt = <1975000>;
103 regulator-name = "sw3a_vddr";
109 regulator-min-microvolt = <400000>;
110 regulator-max-microvolt = <1975000>;
111 regulator-name = "sw3b_vddr";
117 regulator-min-microvolt = <1800000>;
118 regulator-max-microvolt = <3300000>;
119 regulator-name = "gen_rgmii";
123 regulator-min-microvolt = <5000000>;
124 regulator-max-microvolt = <5150000>;
125 regulator-name = "gen_5v0";
129 regulator-min-microvolt = <1000000>;
130 regulator-max-microvolt = <3000000>;
131 regulator-name = "gen_vsns";
142 regulator-min-microvolt = <1500000>;
143 regulator-max-microvolt = <1500000>;
144 regulator-name = "gen_1v5";
148 regulator-name = "vgen2";
149 regulator-min-microvolt = <800000>;
150 regulator-max-microvolt = <1550000>;
154 regulator-name = "gen_vadj_0";
155 regulator-min-microvolt = <3000000>;
156 regulator-max-microvolt = <3000000>;
160 regulator-name = "gen_1v8";
161 regulator-min-microvolt = <1800000>;
162 regulator-max-microvolt = <1800000>;
167 regulator-name = "gen_adj_1";
168 regulator-min-microvolt = <3300000>;
169 regulator-max-microvolt = <3300000>;
174 regulator-name = "gen_2v5";
175 regulator-min-microvolt = <2500000>;
176 regulator-max-microvolt = <2500000>;
181 regulator-min-microvolt = <2500000>;
182 regulator-max-microvolt = <3000000>;
188 temp_sense0: tmp102@4a {
189 compatible = "ti,tmp102";
191 pinctrl-names = "default";
192 pinctrl-0 = <&pinctrl_tempsense>;
193 interrupt-parent = <&gpio6>;
194 interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
195 #thermal-sensor-cells = <1>;
198 temp_sense1: tmp102@49 {
199 compatible = "ti,tmp102";
201 interrupt-parent = <&gpio6>;
202 interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
203 #thermal-sensor-cells = <1>;
206 mfg_eeprom: at24@51 {
207 compatible = "atmel,24c64";
213 user_eeprom: at24@52 {
214 compatible = "atmel,24c64";
221 pinctrl-names = "default";
222 pinctrl-0 = <&pinctrl_hog>;
224 pinctrl_hog: hoggrp {
226 MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x1b0b0
227 MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x1b0b0
228 MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x1b0b0
229 MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x1b0b0
230 MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x1b0b0
231 MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x1b0b0
232 MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x1b0b0
233 MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x1b0b0
234 MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x1b0b0
235 MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x1b0b0
236 MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x1b0b0
237 MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x1b0b0
238 MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x1b0b0
239 MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x1b0b0
240 MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x1b0b0
241 MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x1b0b0
242 MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x1b0b0
243 MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x1b0b0
244 MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x1b0b0
245 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
249 pinctrl_gpmi_nand: gpminandgrp {
251 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
252 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
253 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
254 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000
255 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
256 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
257 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
258 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
259 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
260 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
261 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
262 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
263 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
264 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
265 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
269 pinctrl_i2c3: i2c3grp {
271 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
272 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
276 pinctrl_uart1: uart1grp {
278 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
279 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
283 pinctrl_uart2: uart2grp {
285 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x13059 /* BT_EN */
286 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
287 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
288 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
289 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
293 pinctrl_usdhc1: usdhc1grp {
295 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170B9
296 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100B9
297 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170B9
298 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170B9
299 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170B9
300 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170B9
304 pinctrl_usdhc3: usdhc3grp {
306 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17049
307 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10049
308 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17049
309 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17049
310 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17049
311 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17049
312 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x130b0 /* WL_IRQ */
313 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* WLAN_EN */
317 pinctrl_tempsense: tempsensegrp {
319 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Temp Sense Alert */
329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_uart1>;
335 pinctrl-names = "default";
336 pinctrl-0 = <&pinctrl_uart2>;
340 compatible = "ti,wl1837-st";
341 enable-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
346 pinctrl-names = "default", "state_100mhz", "state_200mhz";
347 pinctrl-0 = <&pinctrl_usdhc1>;
349 keep-power-in-suspend;
352 vmmc-supply = <&sw2_reg>;
356 pinctrl-names = "default";
357 pinctrl-0 = <&pinctrl_usdhc3>;
360 keep-power-in-suspend;
362 vmmc-supply = <®_wl18xx_vmmc>;
364 #address-cells = <1>;
367 compatible = "ti,wl1837";
369 interrupt-parent = <&gpio7>;
370 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
371 tcxo-clock-frequency = <26000000>;