arch/arm/dts/imx6-apalis.dts

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * Copyright 2019 Toradex AG
   4  */
   5
   6 /dts-v1/;
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include "imx6q.dtsi"
   9
  10 / {
  11         model = "Toradex Apalis iMX6Q/D";
  12         compatible = "toradex,apalis_imx6q", "fsl,imx6q";
  13
  14         /* Will be filled by the bootloader */
  15         memory@10000000 {
  16                 device_type = "memory";
  17                 reg = <0x10000000 0>;
  18         };
  19
  20         aliases {
  21                 mmc0 = &usdhc3;
  22                 mmc1 = &usdhc1;
  23                 mmc2 = &usdhc2;
  24                 usb0 = &usbotg; /* required for ums */
  25         };
  26
  27         chosen {
  28                 stdout-path = &uart1;
  29         };
  30
  31         reg_module_3v3: regulator-module-3v3 {
  32                 compatible = "regulator-fixed";
  33                 regulator-name = "+V3.3";
  34                 regulator-min-microvolt = <3300000>;
  35                 regulator-max-microvolt = <3300000>;
  36                 regulator-always-on;
  37         };
  38
  39         reg_usb_otg_vbus: regulator-usb-otg-vbus {
  40                 compatible = "regulator-fixed";
  41                 pinctrl-names = "default";
  42                 pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>;
  43                 regulator-name = "usb_otg_vbus";
  44                 regulator-min-microvolt = <5000000>;
  45                 regulator-max-microvolt = <5000000>;
  46                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* USBO1_EN */
  47                 enable-active-high;
  48         };
  49
  50         /* on-module USB hub */
  51         reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub {
  52                 compatible = "regulator-fixed";
  53                 pinctrl-names = "default";
  54                 pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>;
  55                 regulator-name = "usb_host_vbus_hub";
  56                 regulator-min-microvolt = <5000000>;
  57                 regulator-max-microvolt = <5000000>;
  58                 gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>;
  59                 startup-delay-us = <2000>;
  60                 enable-active-high;
  61         };
  62
  63         reg_usb_host_vbus: regulator-usb-host-vbus {
  64                 compatible = "regulator-fixed";
  65                 pinctrl-names = "default";
  66                 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
  67                 regulator-name = "usb_host_vbus";
  68                 regulator-min-microvolt = <5000000>;
  69                 regulator-max-microvolt = <5000000>;
  70                 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; /* USBH_EN */
  71                 enable-active-high;
  72                 vin-supply = <&reg_usb_host_vbus_hub>;
  73         };
  74 };
  75
  76 /* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
  77 &i2c1 {
  78         clock-frequency = <100000>;
  79         pinctrl-names = "default";
  80         pinctrl-0 = <&pinctrl_i2c1>;
  81         status = "okay";
  82 };
  83
  84 /*
  85  * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
  86  * touch screen controller
  87  */
  88 &i2c2 {
  89         clock-frequency = <100000>;
  90         pinctrl-names = "default";
  91         pinctrl-0 = <&pinctrl_i2c2>;
  92         status = "okay";
  93
  94         pmic: pfuze100@8 {
  95                 compatible = "fsl,pfuze100";
  96                 reg = <0x08>;
  97
  98                 regulators {
  99                         sw1a_reg: sw1ab {
 100                                 regulator-min-microvolt = <300000>;
 101                                 regulator-max-microvolt = <1875000>;
 102                                 regulator-boot-on;
 103                                 regulator-always-on;
 104                                 regulator-ramp-delay = <6250>;
 105                         };
 106
 107                         sw1c_reg: sw1c {
 108                                 regulator-min-microvolt = <300000>;
 109                                 regulator-max-microvolt = <1875000>;
 110                                 regulator-boot-on;
 111                                 regulator-always-on;
 112                                 regulator-ramp-delay = <6250>;
 113                         };
 114
 115                         sw3a_reg: sw3a {
 116                                 regulator-min-microvolt = <400000>;
 117                                 regulator-max-microvolt = <1975000>;
 118                                 regulator-boot-on;
 119                                 regulator-always-on;
 120                         };
 121
 122                         swbst_reg: swbst {
 123                                 regulator-min-microvolt = <5000000>;
 124                                 regulator-max-microvolt = <5150000>;
 125                                 regulator-boot-on;
 126                                 regulator-always-on;
 127                         };
 128
 129                         snvs_reg: vsnvs {
 130                                 regulator-min-microvolt = <1000000>;
 131                                 regulator-max-microvolt = <3000000>;
 132                                 regulator-boot-on;
 133                                 regulator-always-on;
 134                         };
 135
 136                         vref_reg: vrefddr {
 137                                 regulator-boot-on;
 138                                 regulator-always-on;
 139                         };
 140
 141                         vgen1_reg: vgen1 {
 142                                 regulator-min-microvolt = <800000>;
 143                                 regulator-max-microvolt = <1550000>;
 144                                 regulator-boot-on;
 145                                 regulator-always-on;
 146                         };
 147
 148                         vgen2_reg: vgen2 {
 149                                 regulator-min-microvolt = <800000>;
 150                                 regulator-max-microvolt = <1550000>;
 151                                 regulator-boot-on;
 152                                 regulator-always-on;
 153                         };
 154
 155                         vgen3_reg: vgen3 {
 156                                 regulator-min-microvolt = <1800000>;
 157                                 regulator-max-microvolt = <3300000>;
 158                                 regulator-boot-on;
 159                                 regulator-always-on;
 160                         };
 161
 162                         vgen4_reg: vgen4 {
 163                                 regulator-min-microvolt = <1800000>;
 164                                 regulator-max-microvolt = <1800000>;
 165                                 regulator-boot-on;
 166                                 regulator-always-on;
 167                         };
 168
 169                         vgen5_reg: vgen5 {
 170                                 regulator-min-microvolt = <1800000>;
 171                                 regulator-max-microvolt = <3300000>;
 172                                 regulator-boot-on;
 173                                 regulator-always-on;
 174                         };
 175
 176                         vgen6_reg: vgen6 {
 177                                 regulator-min-microvolt = <1800000>;
 178                                 regulator-max-microvolt = <3300000>;
 179                                 regulator-boot-on;
 180                                 regulator-always-on;
 181                         };
 182                 };
 183         };
 184 };
 185
 186 /*
 187  * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
 188  * board)
 189  */
 190 &i2c3 {
 191         clock-frequency = <100000>;
 192         pinctrl-names = "default", "gpio";
 193         pinctrl-0 = <&pinctrl_i2c3>;
 194         pinctrl-1 = <&pinctrl_i2c3_recovery>;
 195         scl-gpios = <&gpio3 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 196         sda-gpios = <&gpio3 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 197         status = "okay";
 198 };
 199
 200 /* Apalis Serial ATA */
 201 &sata {
 202         status = "okay";
 203 };
 204
 205 /* Apalis UART1 */
 206 &uart1 {
 207         pinctrl-names = "default";
 208         pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
 209         fsl,dte-mode;
 210         uart-has-rtscts;
 211         status = "okay";
 212 };
 213
 214 /* Apalis UART2 */
 215 &uart2 {
 216         pinctrl-names = "default";
 217         pinctrl-0 = <&pinctrl_uart2_dte>;
 218         fsl,dte-mode;
 219         uart-has-rtscts;
 220         status = "okay";
 221 };
 222
 223 /* Apalis UART3 */
 224 &uart4 {
 225         pinctrl-names = "default";
 226         pinctrl-0 = <&pinctrl_uart4_dte>;
 227         fsl,dte-mode;
 228         status = "okay";
 229 };
 230
 231 /* Apalis UART4 */
 232 &uart5 {
 233         pinctrl-names = "default";
 234         pinctrl-0 = <&pinctrl_uart5_dte>;
 235         fsl,dte-mode;
 236         status = "okay";
 237 };
 238
 239 /* Apalis USBH[2|3|4] */
 240 &usbh1 {
 241         dr_mode = "host";
 242         vbus-supply = <&reg_usb_host_vbus>;
 243         status = "okay";
 244 };
 245
 246 /* Apalis USBO1 */
 247 &usbotg {
 248         dr_mode = "host";
 249         vbus-supply = <&reg_usb_otg_vbus>;
 250         status = "okay";
 251 };
 252
 253 /* Apalis MMC1 */
 254 &usdhc1 {
 255         pinctrl-names = "default";
 256         pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit &pinctrl_mmc_cd>;
 257         cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; /* MMC1_CD */
 258         disable-wp;
 259         no-1-8-v;
 260         status = "okay";
 261 };
 262
 263 /* Apalis SD1 */
 264 &usdhc2 {
 265         pinctrl-names = "default";
 266         pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>;
 267         cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; /* SD1_CD */
 268         disable-wp;
 269         no-1-8-v;
 270         status = "okay";
 271 };
 272
 273 /* eMMC */
 274 &usdhc3 {
 275         pinctrl-names = "default";
 276         pinctrl-0 = <&pinctrl_usdhc3>;
 277         vqmmc-supply = <&reg_module_3v3>;
 278         bus-width = <8>;
 279         no-1-8-v;
 280         non-removable;
 281         status = "okay";
 282 };
 283
 284 &iomuxc {
 285         pinctrl_apalis_gpio1: gpio2io04grp {
 286                 fsl,pins = <
 287                         MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0
 288                 >;
 289         };
 290
 291         pinctrl_apalis_gpio2: gpio2io05grp {
 292                 fsl,pins = <
 293                         MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0
 294                 >;
 295         };
 296
 297         pinctrl_apalis_gpio3: gpio2io06grp {
 298                 fsl,pins = <
 299                         MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0
 300                 >;
 301         };
 302
 303         pinctrl_apalis_gpio4: gpio2io07grp {
 304                 fsl,pins = <
 305                         MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0
 306                 >;
 307         };
 308
 309         pinctrl_apalis_gpio5: gpio6io10grp {
 310                 fsl,pins = <
 311                         MX6QDL_PAD_NANDF_RB0__GPIO6_IO10        0x130b0
 312                 >;
 313         };
 314
 315         pinctrl_apalis_gpio6: gpio6io09grp {
 316                 fsl,pins = <
 317                         MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09       0x130b0
 318                 >;
 319         };
 320
 321         pinctrl_apalis_gpio7: gpio1io02grp {
 322                 fsl,pins = <
 323                         MX6QDL_PAD_GPIO_2__GPIO1_IO02   0x130b0
 324                 >;
 325         };
 326
 327         pinctrl_apalis_gpio8: gpio1io06grp {
 328                 fsl,pins = <
 329                         MX6QDL_PAD_GPIO_6__GPIO1_IO06   0x130b0
 330                 >;
 331         };
 332
 333         pinctrl_audmux: audmuxgrp {
 334                 fsl,pins = <
 335                         MX6QDL_PAD_DISP0_DAT20__AUD4_TXC        0x130b0
 336                         MX6QDL_PAD_DISP0_DAT21__AUD4_TXD        0x130b0
 337                         MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS       0x130b0
 338                         MX6QDL_PAD_DISP0_DAT23__AUD4_RXD        0x130b0
 339                         /* SGTL5000 sys_mclk */
 340                         MX6QDL_PAD_GPIO_5__CCM_CLKO1            0x130b0
 341                 >;
 342         };
 343
 344         pinctrl_cam_mclk: cammclkgrp {
 345                 fsl,pins = <
 346                         /* CAM sys_mclk */
 347                         MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
 348                 >;
 349         };
 350
 351         pinctrl_ecspi1: ecspi1grp {
 352                 fsl,pins = <
 353                         MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO       0x100b1
 354                         MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI       0x100b1
 355                         MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK       0x100b1
 356                         /* SPI1 cs */
 357                         MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25        0x000b1
 358                 >;
 359         };
 360
 361         pinctrl_ecspi2: ecspi2grp {
 362                 fsl,pins = <
 363                         MX6QDL_PAD_EIM_OE__ECSPI2_MISO  0x100b1
 364                         MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
 365                         MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
 366                         /* SPI2 cs */
 367                         MX6QDL_PAD_EIM_RW__GPIO2_IO26   0x000b1
 368                 >;
 369         };
 370
 371         pinctrl_enet: enetgrp {
 372                 fsl,pins = <
 373                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x100b0
 374                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x100b0
 375                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x10030
 376                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x10030
 377                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x10030
 378                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x10030
 379                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x10030
 380                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x10030
 381                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x100b0
 382                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 383                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 384                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 385                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 386                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 387                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 388                         /* Ethernet PHY reset */
 389                         MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25      0x000b0
 390                         /* Ethernet PHY interrupt */
 391                         MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x000b1
 392                 >;
 393         };
 394
 395         pinctrl_flexcan1: flexcan1grp {
 396                 fsl,pins = <
 397                         MX6QDL_PAD_GPIO_7__FLEXCAN1_TX  0x1b0b0
 398                         MX6QDL_PAD_GPIO_8__FLEXCAN1_RX  0x1b0b0
 399                 >;
 400         };
 401
 402         pinctrl_flexcan2: flexcan2grp {
 403                 fsl,pins = <
 404                         MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX        0x1b0b0
 405                         MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX        0x1b0b0
 406                 >;
 407         };
 408
 409         pinctrl_gpio_bl_on: gpioblon {
 410                 fsl,pins = <
 411                         MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0
 412                 >;
 413         };
 414
 415         pinctrl_gpio_keys: gpio1io04grp {
 416                 fsl,pins = <
 417                         /* Power button */
 418                         MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
 419                 >;
 420         };
 421
 422         pinctrl_hdmi_cec: hdmicecgrp {
 423                 fsl,pins = <
 424                         MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
 425                 >;
 426         };
 427
 428         pinctrl_hdmi_ddc: hdmiddcgrp {
 429                 fsl,pins = <
 430                         MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL     0x4001b8b1
 431                         MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA     0x4001b8b1
 432                 >;
 433         };
 434
 435         pinctrl_i2c1: i2c1grp {
 436                 fsl,pins = <
 437                         MX6QDL_PAD_CSI0_DAT8__I2C1_SDA  0x4001b8b1
 438                         MX6QDL_PAD_CSI0_DAT9__I2C1_SCL  0x4001b8b1
 439                 >;
 440         };
 441
 442         pinctrl_i2c2: i2c2grp {
 443                 fsl,pins = <
 444                         MX6QDL_PAD_KEY_COL3__I2C2_SCL   0x4001b8b1
 445                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA   0x4001b8b1
 446                 >;
 447         };
 448
 449         pinctrl_i2c3: i2c3grp {
 450                 fsl,pins = <
 451                         MX6QDL_PAD_EIM_D17__I2C3_SCL    0x4001b8b1
 452                         MX6QDL_PAD_EIM_D18__I2C3_SDA    0x4001b8b1
 453                 >;
 454         };
 455
 456         pinctrl_i2c3_recovery: i2c3recoverygrp {
 457                 fsl,pins = <
 458                         MX6QDL_PAD_EIM_D17__GPIO3_IO17  0x4001b8b1
 459                         MX6QDL_PAD_EIM_D18__GPIO3_IO18  0x4001b8b1
 460                 >;
 461         };
 462
 463         pinctrl_ipu1_lcdif: ipu1lcdifgrp {
 464                 fsl,pins = <
 465                         MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK   0x61
 466                         /* DE */
 467                         MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15     0x61
 468                         /* HSync */
 469                         MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02     0x61
 470                         /* VSync */
 471                         MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03     0x61
 472                         MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00   0x61
 473                         MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01   0x61
 474                         MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02   0x61
 475                         MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03   0x61
 476                         MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04   0x61
 477                         MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05   0x61
 478                         MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06   0x61
 479                         MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07   0x61
 480                         MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08   0x61
 481                         MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09   0x61
 482                         MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10   0x61
 483                         MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11   0x61
 484                         MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12   0x61
 485                         MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13   0x61
 486                         MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14   0x61
 487                         MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15   0x61
 488                         MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16   0x61
 489                         MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17   0x61
 490                         MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18   0x61
 491                         MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19   0x61
 492                         MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20   0x61
 493                         MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21   0x61
 494                         MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22   0x61
 495                         MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23   0x61
 496                 >;
 497         };
 498
 499         pinctrl_ipu2_vdac: ipu2vdacgrp {
 500                 fsl,pins = <
 501                         MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK      0xd1
 502                         MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15            0xd1
 503                         MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02             0xd1
 504                         MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03             0xd1
 505                         MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00        0xf9
 506                         MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01        0xf9
 507                         MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02        0xf9
 508                         MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03        0xf9
 509                         MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04        0xf9
 510                         MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05        0xf9
 511                         MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06        0xf9
 512                         MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07        0xf9
 513                         MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08        0xf9
 514                         MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09        0xf9
 515                         MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10       0xf9
 516                         MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11       0xf9
 517                         MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12       0xf9
 518                         MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13       0xf9
 519                         MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14       0xf9
 520                         MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15       0xf9
 521                 >;
 522         };
 523
 524         pinctrl_mmc_cd: gpiommccdgrp {
 525                 fsl,pins = <
 526                          /* MMC1 CD */
 527                         MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0
 528                 >;
 529         };
 530
 531         pinctrl_pwm1: pwm1grp {
 532                 fsl,pins = <
 533                         MX6QDL_PAD_GPIO_9__PWM1_OUT     0x1b0b1
 534                 >;
 535         };
 536
 537         pinctrl_pwm2: pwm2grp {
 538                 fsl,pins = <
 539                         MX6QDL_PAD_GPIO_1__PWM2_OUT     0x1b0b1
 540                 >;
 541         };
 542
 543         pinctrl_pwm3: pwm3grp {
 544                 fsl,pins = <
 545                         MX6QDL_PAD_SD4_DAT1__PWM3_OUT   0x1b0b1
 546                 >;
 547         };
 548
 549         pinctrl_pwm4: pwm4grp {
 550                 fsl,pins = <
 551                         MX6QDL_PAD_SD4_DAT2__PWM4_OUT   0x1b0b1
 552                 >;
 553         };
 554
 555         pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
 556                 fsl,pins = <
 557                         /* USBH_EN */
 558                         MX6QDL_PAD_GPIO_0__GPIO1_IO00   0x0f058
 559                 >;
 560         };
 561
 562         pinctrl_regulator_usbhub_pwr: gpioregusbhubpwrgrp {
 563                 fsl,pins = <
 564                         /* USBH_HUB_EN */
 565                         MX6QDL_PAD_EIM_D28__GPIO3_IO28  0x0f058
 566                 >;
 567         };
 568
 569         pinctrl_regulator_usbotg_pwr: gpioregusbotgpwrgrp {
 570                 fsl,pins = <
 571                         /* USBO1 power en */
 572                         MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x0f058
 573                 >;
 574         };
 575
 576         pinctrl_reset_moci: gpioresetmocigrp {
 577                 fsl,pins = <
 578                         /* RESET_MOCI control */
 579                         MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28       0x0f058
 580                 >;
 581         };
 582
 583         pinctrl_sd_cd: gpiosdcdgrp {
 584                 fsl,pins = <
 585                         /* SD1 CD */
 586                         MX6QDL_PAD_NANDF_CS1__GPIO6_IO14        0x000b0
 587                 >;
 588         };
 589
 590         pinctrl_spdif: spdifgrp {
 591                 fsl,pins = <
 592                         MX6QDL_PAD_GPIO_16__SPDIF_IN    0x1b0b0
 593                         MX6QDL_PAD_GPIO_17__SPDIF_OUT   0x1b0b0
 594                 >;
 595         };
 596
 597         pinctrl_touch_int: gpiotouchintgrp {
 598                 fsl,pins = <
 599                         /* STMPE811 interrupt */
 600                         MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
 601                 >;
 602         };
 603
 604         pinctrl_uart1_dce: uart1dcegrp {
 605                 fsl,pins = <
 606                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
 607                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
 608                 >;
 609         };
 610
 611         /* DTE mode */
 612         pinctrl_uart1_dte: uart1dtegrp {
 613                 fsl,pins = <
 614                         MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA    0x1b0b1
 615                         MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA    0x1b0b1
 616                         MX6QDL_PAD_EIM_D19__UART1_RTS_B         0x1b0b1
 617                         MX6QDL_PAD_EIM_D20__UART1_CTS_B         0x1b0b1
 618                 >;
 619         };
 620
 621         /* Additional DTR, DSR, DCD */
 622         pinctrl_uart1_ctrl: uart1ctrlgrp {
 623                 fsl,pins = <
 624                         MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
 625                         MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
 626                         MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
 627                 >;
 628         };
 629
 630         pinctrl_uart2_dce: uart2dcegrp {
 631                 fsl,pins = <
 632                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 633                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 634                 >;
 635         };
 636
 637         /* DTE mode */
 638         pinctrl_uart2_dte: uart2dtegrp {
 639                 fsl,pins = <
 640                         MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA      0x1b0b1
 641                         MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA      0x1b0b1
 642                         MX6QDL_PAD_SD4_DAT6__UART2_RTS_B        0x1b0b1
 643                         MX6QDL_PAD_SD4_DAT5__UART2_CTS_B        0x1b0b1
 644                 >;
 645         };
 646
 647         pinctrl_uart4_dce: uart4dcegrp {
 648                 fsl,pins = <
 649                         MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
 650                         MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
 651                 >;
 652         };
 653
 654         /* DTE mode */
 655         pinctrl_uart4_dte: uart4dtegrp {
 656                 fsl,pins = <
 657                         MX6QDL_PAD_KEY_COL0__UART4_RX_DATA      0x1b0b1
 658                         MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA      0x1b0b1
 659                 >;
 660         };
 661
 662         pinctrl_uart5_dce: uart5dcegrp {
 663                 fsl,pins = <
 664                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 665                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 666                 >;
 667         };
 668
 669         /* DTE mode */
 670         pinctrl_uart5_dte: uart5dtegrp {
 671                 fsl,pins = <
 672                         MX6QDL_PAD_KEY_COL1__UART5_RX_DATA      0x1b0b1
 673                         MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA      0x1b0b1
 674                 >;
 675         };
 676
 677         pinctrl_usbotg: usbotggrp {
 678                 fsl,pins = <
 679                         MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID       0x17059
 680                 >;
 681         };
 682
 683         pinctrl_usdhc1_4bit: usdhc1grp_4bit {
 684                 fsl,pins = <
 685                         MX6QDL_PAD_SD1_CMD__SD1_CMD     0x17071
 686                         MX6QDL_PAD_SD1_CLK__SD1_CLK     0x10071
 687                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0  0x17071
 688                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1  0x17071
 689                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2  0x17071
 690                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3  0x17071
 691                 >;
 692         };
 693
 694         pinctrl_usdhc1_8bit: usdhc1grp_8bit {
 695                 fsl,pins = <
 696                         MX6QDL_PAD_NANDF_D0__SD1_DATA4  0x17071
 697                         MX6QDL_PAD_NANDF_D1__SD1_DATA5  0x17071
 698                         MX6QDL_PAD_NANDF_D2__SD1_DATA6  0x17071
 699                         MX6QDL_PAD_NANDF_D3__SD1_DATA7  0x17071
 700                 >;
 701         };
 702
 703         pinctrl_usdhc2: usdhc2grp {
 704                 fsl,pins = <
 705                         MX6QDL_PAD_SD2_CMD__SD2_CMD     0x17071
 706                         MX6QDL_PAD_SD2_CLK__SD2_CLK     0x10071
 707                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0  0x17071
 708                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1  0x17071
 709                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2  0x17071
 710                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3  0x17071
 711                 >;
 712         };
 713
 714         pinctrl_usdhc3: usdhc3grp {
 715                 fsl,pins = <
 716                         MX6QDL_PAD_SD3_CMD__SD3_CMD     0x17059
 717                         MX6QDL_PAD_SD3_CLK__SD3_CLK     0x10059
 718                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0  0x17059
 719                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1  0x17059
 720                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2  0x17059
 721                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3  0x17059
 722                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4  0x17059
 723                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5  0x17059
 724                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6  0x17059
 725                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7  0x17059
 726                         /* eMMC reset */
 727                         MX6QDL_PAD_SD3_RST__SD3_RESET   0x17059
 728                 >;
 729         };
 730 };