arch/arm/dts/imx53.dtsi

   1 /*
   2  * Copyright 2016 Beckhoff Automation
   3  * Copyright 2011 Freescale Semiconductor, Inc.
   4  * Copyright 2011 Linaro Ltd.
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 #include "skeleton.dtsi"
  15 #include "imx53-pinfunc.h"
  16 #include <dt-bindings/clock/imx5-clock.h>
  17 #include <dt-bindings/gpio/gpio.h>
  18 #include <dt-bindings/input/input.h>
  19 #include <dt-bindings/interrupt-controller/irq.h>
  20
  21 / {
  22         aliases {
  23                 serial1 = &uart2;
  24                 gpio0 = &gpio1;
  25                 gpio1 = &gpio2;
  26                 gpio2 = &gpio3;
  27                 gpio3 = &gpio4;
  28                 gpio4 = &gpio5;
  29                 gpio5 = &gpio6;
  30                 gpio6 = &gpio7;
  31                 i2c0 = &i2c1;
  32                 i2c1 = &i2c2;
  33                 i2c2 = &i2c3;
  34                 ipu0 = &ipu;
  35                 mmc0 = &esdhc1;
  36                 mmc1 = &esdhc2;
  37                 mmc2 = &esdhc3;
  38                 mmc3 = &esdhc4;
  39                 usb1 = &usbh1;
  40         };
  41
  42         tzic: tz-interrupt-controller@fffc000 {
  43                 compatible = "fsl,imx53-tzic", "fsl,tzic";
  44                 interrupt-controller;
  45                 #interrupt-cells = <1>;
  46                 reg = <0x0fffc000 0x4000>;
  47         };
  48
  49         soc {
  50                 #address-cells = <1>;
  51                 #size-cells = <1>;
  52                 compatible = "simple-bus";
  53                 interrupt-parent = <&tzic>;
  54                 ranges;
  55                 u-boot,dm-pre-reloc;
  56
  57                 aips@50000000 { /* AIPS1 */
  58                         compatible = "fsl,aips-bus", "simple-bus";
  59                         #address-cells = <1>;
  60                         #size-cells = <1>;
  61                         reg = <0x50000000 0x10000000>;
  62                         ranges;
  63
  64                         spba@50000000 {
  65                                 compatible = "fsl,spba-bus", "simple-bus";
  66                                 #address-cells = <1>;
  67                                 #size-cells = <1>;
  68                                 reg = <0x50000000 0x40000>;
  69                                 ranges;
  70
  71                                 esdhc1: esdhc@50004000 {
  72                                         compatible = "fsl,imx53-esdhc";
  73                                         reg = <0x50004000 0x4000>;
  74                                         interrupts = <1>;
  75                                         clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
  76                                                  <&clks IMX5_CLK_DUMMY>,
  77                                                  <&clks IMX5_CLK_ESDHC1_PER_GATE>;
  78                                         clock-names = "ipg", "ahb", "per";
  79                                         bus-width = <4>;
  80                                         status = "disabled";
  81                                 };
  82
  83                                 esdhc2: esdhc@50008000 {
  84                                         compatible = "fsl,imx53-esdhc";
  85                                         reg = <0x50008000 0x4000>;
  86                                         interrupts = <2>;
  87                                         clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
  88                                                  <&clks IMX5_CLK_DUMMY>,
  89                                                  <&clks IMX5_CLK_ESDHC2_PER_GATE>;
  90                                         clock-names = "ipg", "ahb", "per";
  91                                         bus-width = <4>;
  92                                         status = "disabled";
  93                                 };
  94
  95                                 esdhc3: esdhc@50020000 {
  96                                         compatible = "fsl,imx53-esdhc";
  97                                         reg = <0x50020000 0x4000>;
  98                                         interrupts = <3>;
  99                                         clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
 100                                                  <&clks IMX5_CLK_DUMMY>,
 101                                                  <&clks IMX5_CLK_ESDHC3_PER_GATE>;
 102                                         clock-names = "ipg", "ahb", "per";
 103                                         bus-width = <4>;
 104                                         status = "disabled";
 105                                 };
 106
 107                                 esdhc4: esdhc@50024000 {
 108                                         compatible = "fsl,imx53-esdhc";
 109                                         reg = <0x50024000 0x4000>;
 110                                         interrupts = <4>;
 111                                         clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
 112                                                  <&clks IMX5_CLK_DUMMY>,
 113                                                  <&clks IMX5_CLK_ESDHC4_PER_GATE>;
 114                                         clock-names = "ipg", "ahb", "per";
 115                                         bus-width = <4>;
 116                                         status = "disabled";
 117                                 };
 118                         };
 119
 120                         iomuxc: iomuxc@53fa8000 {
 121                                 compatible = "fsl,imx53-iomuxc";
 122                                 reg = <0x53fa8000 0x4000>;
 123                         };
 124
 125                         gpr: iomuxc-gpr@53fa8000 {
 126                                 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
 127                                 reg = <0x53fa8000 0xc>;
 128                         };
 129
 130                         uart2: serial@53fc0000 {
 131                                 compatible = "fsl,imx7d-uart", "fsl,imx53-uart", "fsl,imx21-uart";
 132                                 reg = <0x53fc0000 0x4000>;
 133                                 interrupts = <32>;
 134                                 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
 135                                          <&clks IMX5_CLK_UART2_PER_GATE>;
 136                                 clock-names = "ipg", "per";
 137                                 dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
 138                                 dma-names = "rx", "tx";
 139                                 status = "disabled";
 140                         };
 141
 142                         usbh1: usb@53f80200 {
 143                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 144                                 reg = <0x53f80200 0x0200>;
 145                                 interrupts = <14>;
 146                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 147                                 dr_mode = "host";
 148                                 status = "disabled";
 149                         };
 150
 151                         clks: ccm@53fd4000{
 152                                 compatible = "fsl,imx53-ccm";
 153                                 reg = <0x53fd4000 0x4000>;
 154                                 interrupts = <0 71 0x04 0 72 0x04>;
 155                                 #clock-cells = <1>;
 156                         };
 157
 158                         gpio1: gpio@53f84000 {
 159                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 160                                 reg = <0x53f84000 0x4000>;
 161                                 interrupts = <50 51>;
 162                                 gpio-controller;
 163                                 #gpio-cells = <2>;
 164                                 interrupt-controller;
 165                                 #interrupt-cells = <2>;
 166                         };
 167
 168                         gpio2: gpio@53f88000 {
 169                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 170                                 reg = <0x53f88000 0x4000>;
 171                                 interrupts = <52 53>;
 172                                 gpio-controller;
 173                                 #gpio-cells = <2>;
 174                                 interrupt-controller;
 175                                 #interrupt-cells = <2>;
 176                         };
 177
 178                         gpio3: gpio@53f8c000 {
 179                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 180                                 reg = <0x53f8c000 0x4000>;
 181                                 interrupts = <54 55>;
 182                                 gpio-controller;
 183                                 #gpio-cells = <2>;
 184                                 interrupt-controller;
 185                                 #interrupt-cells = <2>;
 186                         };
 187
 188                         gpio4: gpio@53f90000 {
 189                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 190                                 reg = <0x53f90000 0x4000>;
 191                                 interrupts = <56 57>;
 192                                 gpio-controller;
 193                                 #gpio-cells = <2>;
 194                                 interrupt-controller;
 195                                 #interrupt-cells = <2>;
 196                         };
 197
 198                         gpio5: gpio@53fdc000 {
 199                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 200                                 reg = <0x53fdc000 0x4000>;
 201                                 interrupts = <103 104>;
 202                                 gpio-controller;
 203                                 #gpio-cells = <2>;
 204                                 interrupt-controller;
 205                                 #interrupt-cells = <2>;
 206                         };
 207
 208                         gpio6: gpio@53fe0000 {
 209                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 210                                 reg = <0x53fe0000 0x4000>;
 211                                 interrupts = <105 106>;
 212                                 gpio-controller;
 213                                 #gpio-cells = <2>;
 214                                 interrupt-controller;
 215                                 #interrupt-cells = <2>;
 216                         };
 217
 218                         gpio7: gpio@53fe4000 {
 219                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 220                                 reg = <0x53fe4000 0x4000>;
 221                                 interrupts = <107 108>;
 222                                 gpio-controller;
 223                                 #gpio-cells = <2>;
 224                                 interrupt-controller;
 225                                 #interrupt-cells = <2>;
 226                         };
 227
 228                         i2c3: i2c@53fec000 {
 229                                 #address-cells = <1>;
 230                                 #size-cells = <0>;
 231                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 232                                 reg = <0x53fec000 0x4000>;
 233                                 interrupts = <64>;
 234                                 clocks = <&clks IMX5_CLK_I2C3_GATE>;
 235                                 status = "disabled";
 236                         };
 237                 };
 238
 239                 aips@60000000 { /* AIPS2 */
 240                         compatible = "fsl,aips-bus", "simple-bus";
 241                         #address-cells = <1>;
 242                         #size-cells = <1>;
 243                         reg = <0x60000000 0x10000000>;
 244                         ranges;
 245
 246                         sdma: sdma@63fb0000 {
 247                                 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
 248                                 reg = <0x63fb0000 0x4000>;
 249                                 interrupts = <6>;
 250                                 clocks = <&clks IMX5_CLK_SDMA_GATE>,
 251                                          <&clks IMX5_CLK_SDMA_GATE>;
 252                                 clock-names = "ipg", "ahb";
 253                                 #dma-cells = <3>;
 254                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
 255                         };
 256
 257                         fec: ethernet@63fec000 {
 258                                 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
 259                                 reg = <0x63fec000 0x4000>;
 260                                 interrupts = <87>;
 261                                 clocks = <&clks IMX5_CLK_FEC_GATE>,
 262                                          <&clks IMX5_CLK_FEC_GATE>,
 263                                          <&clks IMX5_CLK_FEC_GATE>;
 264                                 clock-names = "ipg", "ahb", "ptp";
 265                                 status = "disabled";
 266                         };
 267
 268                         i2c2: i2c@63fc4000 {
 269                                 #address-cells = <1>;
 270                                 #size-cells = <0>;
 271                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 272                                 reg = <0x63fc4000 0x4000>;
 273                                 interrupts = <63>;
 274                                 clocks = <&clks IMX5_CLK_I2C2_GATE>;
 275                                 status = "disabled";
 276                         };
 277
 278                         i2c1: i2c@63fc8000 {
 279                                 #address-cells = <1>;
 280                                 #size-cells = <0>;
 281                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 282                                 reg = <0x63fc8000 0x4000>;
 283                                 interrupts = <62>;
 284                                 clocks = <&clks IMX5_CLK_I2C1_GATE>;
 285                                 status = "disabled";
 286                         };
 287                 };
 288
 289                 ipu: ipu@18000000 {
 290                         #address-cells = <1>;
 291                         #size-cells = <0>;
 292                         compatible = "fsl,imx53-ipu";
 293                         reg = <0x18000000 0x08000000>;
 294                         interrupts = <11 10>;
 295                         clocks = <&clks IMX5_CLK_IPU_GATE>,
 296                                  <&clks IMX5_CLK_IPU_DI0_GATE>,
 297                                  <&clks IMX5_CLK_IPU_DI1_GATE>;
 298                         clock-names = "bus", "di0", "di1";
 299                         resets = <&src 2>;
 300                         u-boot,dm-pre-reloc;
 301
 302                         ipu_csi0: port@0 {
 303                                 reg = <0>;
 304                         };
 305
 306                         ipu_csi1: port@1 {
 307                                 reg = <1>;
 308                         };
 309
 310                         ipu_di0: port@2 {
 311                                 #address-cells = <1>;
 312                                 #size-cells = <0>;
 313                                 reg = <2>;
 314
 315                                 ipu_di0_disp0: endpoint@0 {
 316                                         reg = <0>;
 317                                 };
 318
 319                                 ipu_di0_lvds0: endpoint@1 {
 320                                         reg = <1>;
 321                                         remote-endpoint = <&lvds0_in>;
 322                                 };
 323                         };
 324
 325                         ipu_di1: port@3 {
 326                                 #address-cells = <1>;
 327                                 #size-cells = <0>;
 328                                 reg = <3>;
 329
 330                                 ipu_di1_disp1: endpoint@0 {
 331                                         reg = <0>;
 332                                 };
 333
 334                                 ipu_di1_lvds1: endpoint@1 {
 335                                         reg = <1>;
 336                                         remote-endpoint = <&lvds1_in>;
 337                                 };
 338
 339                                 ipu_di1_tve: endpoint@2 {
 340                                         reg = <2>;
 341                                         remote-endpoint = <&tve_in>;
 342                                 };
 343                         };
 344                 };
 345
 346                 tve: tve@63ff0000 {
 347                                 compatible = "fsl,imx53-tve";
 348                                 reg = <0x63ff0000 0x1000>;
 349                                 interrupts = <92>;
 350                                 clocks = <&clks IMX5_CLK_TVE_GATE>,
 351                                          <&clks IMX5_CLK_IPU_DI1_SEL>;
 352                                 clock-names = "tve", "di_sel";
 353                                 status = "disabled";
 354
 355                                 port {
 356                                         tve_in: endpoint {
 357                                                 remote-endpoint = <&ipu_di1_tve>;
 358                                         };
 359                                 };
 360                 };
 361
 362                 src: src@53fd0000 {
 363                                 compatible = "fsl,imx53-src", "fsl,imx51-src";
 364                                 reg = <0x53fd0000 0x4000>;
 365                                 #reset-cells = <1>;
 366                 };
 367
 368                 ldb: ldb@53fa8008 {
 369                                 #address-cells = <1>;
 370                                 #size-cells = <0>;
 371                                 compatible = "fsl,imx53-ldb";
 372                                 reg = <0x53fa8008 0x4>;
 373                                 gpr = <&gpr>;
 374                                 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
 375                                          <&clks IMX5_CLK_LDB_DI1_SEL>,
 376                                          <&clks IMX5_CLK_IPU_DI0_SEL>,
 377                                          <&clks IMX5_CLK_IPU_DI1_SEL>,
 378                                          <&clks IMX5_CLK_LDB_DI0_GATE>,
 379                                          <&clks IMX5_CLK_LDB_DI1_GATE>;
 380                                 clock-names = "di0_pll", "di1_pll",
 381                                               "di0_sel", "di1_sel",
 382                                               "di0", "di1";
 383                                 status = "disabled";
 384
 385                                 lvds-channel@0 {
 386                                         #address-cells = <1>;
 387                                         #size-cells = <0>;
 388                                         reg = <0>;
 389                                         status = "disabled";
 390
 391                                         port@0 {
 392                                                 reg = <0>;
 393
 394                                                 lvds0_in: endpoint {
 395                                                         remote-endpoint = <&ipu_di0_lvds0>;
 396                                                 };
 397                                         };
 398
 399                                         port@2 {
 400                                                 reg = <2>;
 401                                         };
 402                                 };
 403
 404                                 lvds-channel@1 {
 405                                         #address-cells = <1>;
 406                                         #size-cells = <0>;
 407                                         reg = <1>;
 408                                         status = "disabled";
 409
 410                                         port@1 {
 411                                                 reg = <1>;
 412
 413                                                 lvds1_in: endpoint {
 414                                                         remote-endpoint = <&ipu_di1_lvds1>;
 415                                                 };
 416                                         };
 417
 418                                         port@2 {
 419                                                 reg = <2>;
 420                                         };
 421                                 };
 422                 };
 423         };
 424 };