2 * Copyright 2016 Beckhoff Automation
3 * Copyright 2011 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 #include "skeleton.dtsi"
15 #include "imx53-pinfunc.h"
16 #include <dt-bindings/clock/imx5-clock.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/input/input.h>
19 #include <dt-bindings/interrupt-controller/irq.h>
41 tzic: tz-interrupt-controller@fffc000 {
42 compatible = "fsl,imx53-tzic", "fsl,tzic";
44 #interrupt-cells = <1>;
45 reg = <0x0fffc000 0x4000>;
51 compatible = "simple-bus";
52 interrupt-parent = <&tzic>;
55 aips@50000000 { /* AIPS1 */
56 compatible = "fsl,aips-bus", "simple-bus";
59 reg = <0x50000000 0x10000000>;
63 compatible = "fsl,spba-bus", "simple-bus";
66 reg = <0x50000000 0x40000>;
69 esdhc1: esdhc@50004000 {
70 compatible = "fsl,imx53-esdhc";
71 reg = <0x50004000 0x4000>;
73 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
74 <&clks IMX5_CLK_DUMMY>,
75 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
76 clock-names = "ipg", "ahb", "per";
81 esdhc2: esdhc@50008000 {
82 compatible = "fsl,imx53-esdhc";
83 reg = <0x50008000 0x4000>;
85 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
86 <&clks IMX5_CLK_DUMMY>,
87 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
88 clock-names = "ipg", "ahb", "per";
93 esdhc3: esdhc@50020000 {
94 compatible = "fsl,imx53-esdhc";
95 reg = <0x50020000 0x4000>;
97 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
98 <&clks IMX5_CLK_DUMMY>,
99 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
100 clock-names = "ipg", "ahb", "per";
105 esdhc4: esdhc@50024000 {
106 compatible = "fsl,imx53-esdhc";
107 reg = <0x50024000 0x4000>;
109 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
110 <&clks IMX5_CLK_DUMMY>,
111 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
112 clock-names = "ipg", "ahb", "per";
118 iomuxc: iomuxc@53fa8000 {
119 compatible = "fsl,imx53-iomuxc";
120 reg = <0x53fa8000 0x4000>;
123 gpr: iomuxc-gpr@53fa8000 {
124 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
125 reg = <0x53fa8000 0xc>;
128 uart2: serial@53fc0000 {
129 compatible = "fsl,imx7d-uart", "fsl,imx53-uart", "fsl,imx21-uart";
130 reg = <0x53fc0000 0x4000>;
132 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
133 <&clks IMX5_CLK_UART2_PER_GATE>;
134 clock-names = "ipg", "per";
135 dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
136 dma-names = "rx", "tx";
140 usbh1: usb@53f80200 {
141 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
142 reg = <0x53f80200 0x0200>;
144 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
150 compatible = "fsl,imx53-ccm";
151 reg = <0x53fd4000 0x4000>;
152 interrupts = <0 71 0x04 0 72 0x04>;
156 gpio1: gpio@53f84000 {
157 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
158 reg = <0x53f84000 0x4000>;
159 interrupts = <50 51>;
162 interrupt-controller;
163 #interrupt-cells = <2>;
166 gpio2: gpio@53f88000 {
167 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
168 reg = <0x53f88000 0x4000>;
169 interrupts = <52 53>;
172 interrupt-controller;
173 #interrupt-cells = <2>;
176 gpio3: gpio@53f8c000 {
177 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
178 reg = <0x53f8c000 0x4000>;
179 interrupts = <54 55>;
182 interrupt-controller;
183 #interrupt-cells = <2>;
186 gpio4: gpio@53f90000 {
187 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
188 reg = <0x53f90000 0x4000>;
189 interrupts = <56 57>;
192 interrupt-controller;
193 #interrupt-cells = <2>;
196 gpio5: gpio@53fdc000 {
197 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
198 reg = <0x53fdc000 0x4000>;
199 interrupts = <103 104>;
202 interrupt-controller;
203 #interrupt-cells = <2>;
206 gpio6: gpio@53fe0000 {
207 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
208 reg = <0x53fe0000 0x4000>;
209 interrupts = <105 106>;
212 interrupt-controller;
213 #interrupt-cells = <2>;
216 gpio7: gpio@53fe4000 {
217 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
218 reg = <0x53fe4000 0x4000>;
219 interrupts = <107 108>;
222 interrupt-controller;
223 #interrupt-cells = <2>;
227 #address-cells = <1>;
229 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
230 reg = <0x53fec000 0x4000>;
232 clocks = <&clks IMX5_CLK_I2C3_GATE>;
237 aips@60000000 { /* AIPS2 */
238 compatible = "fsl,aips-bus", "simple-bus";
239 #address-cells = <1>;
241 reg = <0x60000000 0x10000000>;
244 sdma: sdma@63fb0000 {
245 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
246 reg = <0x63fb0000 0x4000>;
248 clocks = <&clks IMX5_CLK_SDMA_GATE>,
249 <&clks IMX5_CLK_SDMA_GATE>;
250 clock-names = "ipg", "ahb";
252 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
255 fec: ethernet@63fec000 {
256 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
257 reg = <0x63fec000 0x4000>;
259 clocks = <&clks IMX5_CLK_FEC_GATE>,
260 <&clks IMX5_CLK_FEC_GATE>,
261 <&clks IMX5_CLK_FEC_GATE>;
262 clock-names = "ipg", "ahb", "ptp";
267 #address-cells = <1>;
269 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
270 reg = <0x63fc4000 0x4000>;
272 clocks = <&clks IMX5_CLK_I2C2_GATE>;
277 #address-cells = <1>;
279 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
280 reg = <0x63fc8000 0x4000>;
282 clocks = <&clks IMX5_CLK_I2C1_GATE>;