2 * Copyright 2016 Beckhoff Automation
3 * Copyright 2011 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 #include "skeleton.dtsi"
15 #include "imx53-pinfunc.h"
16 #include <dt-bindings/clock/imx5-clock.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/input/input.h>
19 #include <dt-bindings/interrupt-controller/irq.h>
40 tzic: tz-interrupt-controller@fffc000 {
41 compatible = "fsl,imx53-tzic", "fsl,tzic";
43 #interrupt-cells = <1>;
44 reg = <0x0fffc000 0x4000>;
50 compatible = "simple-bus";
51 interrupt-parent = <&tzic>;
54 aips@50000000 { /* AIPS1 */
55 compatible = "fsl,aips-bus", "simple-bus";
58 reg = <0x50000000 0x10000000>;
62 compatible = "fsl,spba-bus", "simple-bus";
65 reg = <0x50000000 0x40000>;
68 esdhc1: esdhc@50004000 {
69 compatible = "fsl,imx53-esdhc";
70 reg = <0x50004000 0x4000>;
72 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
73 <&clks IMX5_CLK_DUMMY>,
74 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
75 clock-names = "ipg", "ahb", "per";
80 esdhc2: esdhc@50008000 {
81 compatible = "fsl,imx53-esdhc";
82 reg = <0x50008000 0x4000>;
84 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
85 <&clks IMX5_CLK_DUMMY>,
86 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
87 clock-names = "ipg", "ahb", "per";
92 esdhc3: esdhc@50020000 {
93 compatible = "fsl,imx53-esdhc";
94 reg = <0x50020000 0x4000>;
96 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
97 <&clks IMX5_CLK_DUMMY>,
98 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
99 clock-names = "ipg", "ahb", "per";
104 esdhc4: esdhc@50024000 {
105 compatible = "fsl,imx53-esdhc";
106 reg = <0x50024000 0x4000>;
108 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
109 <&clks IMX5_CLK_DUMMY>,
110 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
111 clock-names = "ipg", "ahb", "per";
117 iomuxc: iomuxc@53fa8000 {
118 compatible = "fsl,imx53-iomuxc";
119 reg = <0x53fa8000 0x4000>;
122 gpr: iomuxc-gpr@53fa8000 {
123 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
124 reg = <0x53fa8000 0xc>;
127 uart2: serial@53fc0000 {
128 compatible = "fsl,imx7d-uart", "fsl,imx53-uart", "fsl,imx21-uart";
129 reg = <0x53fc0000 0x4000>;
131 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
132 <&clks IMX5_CLK_UART2_PER_GATE>;
133 clock-names = "ipg", "per";
134 dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
135 dma-names = "rx", "tx";
140 compatible = "fsl,imx53-ccm";
141 reg = <0x53fd4000 0x4000>;
142 interrupts = <0 71 0x04 0 72 0x04>;
146 gpio1: gpio@53f84000 {
147 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
148 reg = <0x53f84000 0x4000>;
149 interrupts = <50 51>;
152 interrupt-controller;
153 #interrupt-cells = <2>;
156 gpio2: gpio@53f88000 {
157 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
158 reg = <0x53f88000 0x4000>;
159 interrupts = <52 53>;
162 interrupt-controller;
163 #interrupt-cells = <2>;
166 gpio3: gpio@53f8c000 {
167 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
168 reg = <0x53f8c000 0x4000>;
169 interrupts = <54 55>;
172 interrupt-controller;
173 #interrupt-cells = <2>;
176 gpio4: gpio@53f90000 {
177 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
178 reg = <0x53f90000 0x4000>;
179 interrupts = <56 57>;
182 interrupt-controller;
183 #interrupt-cells = <2>;
186 gpio5: gpio@53fdc000 {
187 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
188 reg = <0x53fdc000 0x4000>;
189 interrupts = <103 104>;
192 interrupt-controller;
193 #interrupt-cells = <2>;
196 gpio6: gpio@53fe0000 {
197 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
198 reg = <0x53fe0000 0x4000>;
199 interrupts = <105 106>;
202 interrupt-controller;
203 #interrupt-cells = <2>;
206 gpio7: gpio@53fe4000 {
207 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
208 reg = <0x53fe4000 0x4000>;
209 interrupts = <107 108>;
212 interrupt-controller;
213 #interrupt-cells = <2>;
217 #address-cells = <1>;
219 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
220 reg = <0x53fec000 0x4000>;
222 clocks = <&clks IMX5_CLK_I2C3_GATE>;
227 aips@60000000 { /* AIPS2 */
228 compatible = "fsl,aips-bus", "simple-bus";
229 #address-cells = <1>;
231 reg = <0x60000000 0x10000000>;
234 sdma: sdma@63fb0000 {
235 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
236 reg = <0x63fb0000 0x4000>;
238 clocks = <&clks IMX5_CLK_SDMA_GATE>,
239 <&clks IMX5_CLK_SDMA_GATE>;
240 clock-names = "ipg", "ahb";
242 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
245 fec: ethernet@63fec000 {
246 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
247 reg = <0x63fec000 0x4000>;
249 clocks = <&clks IMX5_CLK_FEC_GATE>,
250 <&clks IMX5_CLK_FEC_GATE>,
251 <&clks IMX5_CLK_FEC_GATE>;
252 clock-names = "ipg", "ahb", "ptp";
257 #address-cells = <1>;
259 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
260 reg = <0x63fc4000 0x4000>;
262 clocks = <&clks IMX5_CLK_I2C2_GATE>;
267 #address-cells = <1>;
269 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
270 reg = <0x63fc8000 0x4000>;
272 clocks = <&clks IMX5_CLK_I2C1_GATE>;