arch/arm/dts/imx53.dtsi

   1 /*
   2  * Copyright 2016 Beckhoff Automation
   3  * Copyright 2011 Freescale Semiconductor, Inc.
   4  * Copyright 2011 Linaro Ltd.
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 #include "skeleton.dtsi"
  15 #include "imx53-pinfunc.h"
  16 #include <dt-bindings/clock/imx5-clock.h>
  17 #include <dt-bindings/gpio/gpio.h>
  18 #include <dt-bindings/input/input.h>
  19 #include <dt-bindings/interrupt-controller/irq.h>
  20
  21 / {
  22         aliases {
  23                 serial1 = &uart2;
  24                 gpio0 = &gpio1;
  25                 gpio1 = &gpio2;
  26                 gpio2 = &gpio3;
  27                 gpio3 = &gpio4;
  28                 gpio4 = &gpio5;
  29                 gpio5 = &gpio6;
  30                 gpio6 = &gpio7;
  31                 i2c0 = &i2c1;
  32                 i2c1 = &i2c2;
  33                 i2c2 = &i2c3;
  34                 mmc0 = &esdhc1;
  35                 mmc1 = &esdhc2;
  36                 mmc2 = &esdhc3;
  37                 mmc3 = &esdhc4;
  38         };
  39
  40         tzic: tz-interrupt-controller@fffc000 {
  41                 compatible = "fsl,imx53-tzic", "fsl,tzic";
  42                 interrupt-controller;
  43                 #interrupt-cells = <1>;
  44                 reg = <0x0fffc000 0x4000>;
  45         };
  46
  47         soc {
  48                 #address-cells = <1>;
  49                 #size-cells = <1>;
  50                 compatible = "simple-bus";
  51                 interrupt-parent = <&tzic>;
  52                 ranges;
  53
  54                 aips@50000000 { /* AIPS1 */
  55                         compatible = "fsl,aips-bus", "simple-bus";
  56                         #address-cells = <1>;
  57                         #size-cells = <1>;
  58                         reg = <0x50000000 0x10000000>;
  59                         ranges;
  60
  61                         spba@50000000 {
  62                                 compatible = "fsl,spba-bus", "simple-bus";
  63                                 #address-cells = <1>;
  64                                 #size-cells = <1>;
  65                                 reg = <0x50000000 0x40000>;
  66                                 ranges;
  67
  68                                 esdhc1: esdhc@50004000 {
  69                                         compatible = "fsl,imx53-esdhc";
  70                                         reg = <0x50004000 0x4000>;
  71                                         interrupts = <1>;
  72                                         clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
  73                                                  <&clks IMX5_CLK_DUMMY>,
  74                                                  <&clks IMX5_CLK_ESDHC1_PER_GATE>;
  75                                         clock-names = "ipg", "ahb", "per";
  76                                         bus-width = <4>;
  77                                         status = "disabled";
  78                                 };
  79
  80                                 esdhc2: esdhc@50008000 {
  81                                         compatible = "fsl,imx53-esdhc";
  82                                         reg = <0x50008000 0x4000>;
  83                                         interrupts = <2>;
  84                                         clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
  85                                                  <&clks IMX5_CLK_DUMMY>,
  86                                                  <&clks IMX5_CLK_ESDHC2_PER_GATE>;
  87                                         clock-names = "ipg", "ahb", "per";
  88                                         bus-width = <4>;
  89                                         status = "disabled";
  90                                 };
  91
  92                                 esdhc3: esdhc@50020000 {
  93                                         compatible = "fsl,imx53-esdhc";
  94                                         reg = <0x50020000 0x4000>;
  95                                         interrupts = <3>;
  96                                         clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
  97                                                  <&clks IMX5_CLK_DUMMY>,
  98                                                  <&clks IMX5_CLK_ESDHC3_PER_GATE>;
  99                                         clock-names = "ipg", "ahb", "per";
 100                                         bus-width = <4>;
 101                                         status = "disabled";
 102                                 };
 103
 104                                 esdhc4: esdhc@50024000 {
 105                                         compatible = "fsl,imx53-esdhc";
 106                                         reg = <0x50024000 0x4000>;
 107                                         interrupts = <4>;
 108                                         clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
 109                                                  <&clks IMX5_CLK_DUMMY>,
 110                                                  <&clks IMX5_CLK_ESDHC4_PER_GATE>;
 111                                         clock-names = "ipg", "ahb", "per";
 112                                         bus-width = <4>;
 113                                         status = "disabled";
 114                                 };
 115                         };
 116
 117                         iomuxc: iomuxc@53fa8000 {
 118                                 compatible = "fsl,imx53-iomuxc";
 119                                 reg = <0x53fa8000 0x4000>;
 120                         };
 121
 122                         gpr: iomuxc-gpr@53fa8000 {
 123                                 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
 124                                 reg = <0x53fa8000 0xc>;
 125                         };
 126
 127                         uart2: serial@53fc0000 {
 128                                 compatible = "fsl,imx7d-uart", "fsl,imx53-uart", "fsl,imx21-uart";
 129                                 reg = <0x53fc0000 0x4000>;
 130                                 interrupts = <32>;
 131                                 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
 132                                          <&clks IMX5_CLK_UART2_PER_GATE>;
 133                                 clock-names = "ipg", "per";
 134                                 dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
 135                                 dma-names = "rx", "tx";
 136                                 status = "disabled";
 137                         };
 138
 139                         clks: ccm@53fd4000{
 140                                 compatible = "fsl,imx53-ccm";
 141                                 reg = <0x53fd4000 0x4000>;
 142                                 interrupts = <0 71 0x04 0 72 0x04>;
 143                                 #clock-cells = <1>;
 144                         };
 145
 146                         gpio1: gpio@53f84000 {
 147                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 148                                 reg = <0x53f84000 0x4000>;
 149                                 interrupts = <50 51>;
 150                                 gpio-controller;
 151                                 #gpio-cells = <2>;
 152                                 interrupt-controller;
 153                                 #interrupt-cells = <2>;
 154                         };
 155
 156                         gpio2: gpio@53f88000 {
 157                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 158                                 reg = <0x53f88000 0x4000>;
 159                                 interrupts = <52 53>;
 160                                 gpio-controller;
 161                                 #gpio-cells = <2>;
 162                                 interrupt-controller;
 163                                 #interrupt-cells = <2>;
 164                         };
 165
 166                         gpio3: gpio@53f8c000 {
 167                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 168                                 reg = <0x53f8c000 0x4000>;
 169                                 interrupts = <54 55>;
 170                                 gpio-controller;
 171                                 #gpio-cells = <2>;
 172                                 interrupt-controller;
 173                                 #interrupt-cells = <2>;
 174                         };
 175
 176                         gpio4: gpio@53f90000 {
 177                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 178                                 reg = <0x53f90000 0x4000>;
 179                                 interrupts = <56 57>;
 180                                 gpio-controller;
 181                                 #gpio-cells = <2>;
 182                                 interrupt-controller;
 183                                 #interrupt-cells = <2>;
 184                         };
 185
 186                         gpio5: gpio@53fdc000 {
 187                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 188                                 reg = <0x53fdc000 0x4000>;
 189                                 interrupts = <103 104>;
 190                                 gpio-controller;
 191                                 #gpio-cells = <2>;
 192                                 interrupt-controller;
 193                                 #interrupt-cells = <2>;
 194                         };
 195
 196                         gpio6: gpio@53fe0000 {
 197                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 198                                 reg = <0x53fe0000 0x4000>;
 199                                 interrupts = <105 106>;
 200                                 gpio-controller;
 201                                 #gpio-cells = <2>;
 202                                 interrupt-controller;
 203                                 #interrupt-cells = <2>;
 204                         };
 205
 206                         gpio7: gpio@53fe4000 {
 207                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 208                                 reg = <0x53fe4000 0x4000>;
 209                                 interrupts = <107 108>;
 210                                 gpio-controller;
 211                                 #gpio-cells = <2>;
 212                                 interrupt-controller;
 213                                 #interrupt-cells = <2>;
 214                         };
 215
 216                         i2c3: i2c@53fec000 {
 217                                 #address-cells = <1>;
 218                                 #size-cells = <0>;
 219                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 220                                 reg = <0x53fec000 0x4000>;
 221                                 interrupts = <64>;
 222                                 clocks = <&clks IMX5_CLK_I2C3_GATE>;
 223                                 status = "disabled";
 224                         };
 225                 };
 226
 227                 aips@60000000 { /* AIPS2 */
 228                         compatible = "fsl,aips-bus", "simple-bus";
 229                         #address-cells = <1>;
 230                         #size-cells = <1>;
 231                         reg = <0x60000000 0x10000000>;
 232                         ranges;
 233
 234                         sdma: sdma@63fb0000 {
 235                                 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
 236                                 reg = <0x63fb0000 0x4000>;
 237                                 interrupts = <6>;
 238                                 clocks = <&clks IMX5_CLK_SDMA_GATE>,
 239                                          <&clks IMX5_CLK_SDMA_GATE>;
 240                                 clock-names = "ipg", "ahb";
 241                                 #dma-cells = <3>;
 242                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
 243                         };
 244
 245                         fec: ethernet@63fec000 {
 246                                 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
 247                                 reg = <0x63fec000 0x4000>;
 248                                 interrupts = <87>;
 249                                 clocks = <&clks IMX5_CLK_FEC_GATE>,
 250                                          <&clks IMX5_CLK_FEC_GATE>,
 251                                          <&clks IMX5_CLK_FEC_GATE>;
 252                                 clock-names = "ipg", "ahb", "ptp";
 253                                 status = "disabled";
 254                         };
 255
 256                         i2c2: i2c@63fc4000 {
 257                                 #address-cells = <1>;
 258                                 #size-cells = <0>;
 259                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 260                                 reg = <0x63fc4000 0x4000>;
 261                                 interrupts = <63>;
 262                                 clocks = <&clks IMX5_CLK_I2C2_GATE>;
 263                                 status = "disabled";
 264                         };
 265
 266                         i2c1: i2c@63fc8000 {
 267                                 #address-cells = <1>;
 268                                 #size-cells = <0>;
 269                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 270                                 reg = <0x63fc8000 0x4000>;
 271                                 interrupts = <62>;
 272                                 clocks = <&clks IMX5_CLK_I2C1_GATE>;
 273                                 status = "disabled";
 274                         };
 275                 };
 276         };
 277 };