2 * Copyright 2016 Beckhoff Automation
3 * Copyright 2011 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 #include "skeleton.dtsi"
15 #include "imx53-pinfunc.h"
16 #include <dt-bindings/clock/imx5-clock.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/input/input.h>
19 #include <dt-bindings/interrupt-controller/irq.h>
38 tzic: tz-interrupt-controller@fffc000 {
39 compatible = "fsl,imx53-tzic", "fsl,tzic";
41 #interrupt-cells = <1>;
42 reg = <0x0fffc000 0x4000>;
48 compatible = "simple-bus";
49 interrupt-parent = <&tzic>;
52 aips@50000000 { /* AIPS1 */
53 compatible = "fsl,aips-bus", "simple-bus";
56 reg = <0x50000000 0x10000000>;
60 compatible = "fsl,spba-bus", "simple-bus";
63 reg = <0x50000000 0x40000>;
66 esdhc1: esdhc@50004000 {
67 compatible = "fsl,imx53-esdhc";
68 reg = <0x50004000 0x4000>;
70 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
71 <&clks IMX5_CLK_DUMMY>,
72 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
73 clock-names = "ipg", "ahb", "per";
78 esdhc2: esdhc@50008000 {
79 compatible = "fsl,imx53-esdhc";
80 reg = <0x50008000 0x4000>;
82 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
83 <&clks IMX5_CLK_DUMMY>,
84 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
85 clock-names = "ipg", "ahb", "per";
91 iomuxc: iomuxc@53fa8000 {
92 compatible = "fsl,imx53-iomuxc";
93 reg = <0x53fa8000 0x4000>;
96 gpr: iomuxc-gpr@53fa8000 {
97 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
98 reg = <0x53fa8000 0xc>;
101 uart2: serial@53fc0000 {
102 compatible = "fsl,imx7d-uart", "fsl,imx53-uart", "fsl,imx21-uart";
103 reg = <0x53fc0000 0x4000>;
105 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
106 <&clks IMX5_CLK_UART2_PER_GATE>;
107 clock-names = "ipg", "per";
108 dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
109 dma-names = "rx", "tx";
114 compatible = "fsl,imx53-ccm";
115 reg = <0x53fd4000 0x4000>;
116 interrupts = <0 71 0x04 0 72 0x04>;
120 gpio1: gpio@53f84000 {
121 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
122 reg = <0x53f84000 0x4000>;
123 interrupts = <50 51>;
126 interrupt-controller;
127 #interrupt-cells = <2>;
130 gpio2: gpio@53f88000 {
131 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
132 reg = <0x53f88000 0x4000>;
133 interrupts = <52 53>;
136 interrupt-controller;
137 #interrupt-cells = <2>;
140 gpio3: gpio@53f8c000 {
141 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
142 reg = <0x53f8c000 0x4000>;
143 interrupts = <54 55>;
146 interrupt-controller;
147 #interrupt-cells = <2>;
150 gpio4: gpio@53f90000 {
151 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
152 reg = <0x53f90000 0x4000>;
153 interrupts = <56 57>;
156 interrupt-controller;
157 #interrupt-cells = <2>;
160 gpio5: gpio@53fdc000 {
161 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
162 reg = <0x53fdc000 0x4000>;
163 interrupts = <103 104>;
166 interrupt-controller;
167 #interrupt-cells = <2>;
170 gpio6: gpio@53fe0000 {
171 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
172 reg = <0x53fe0000 0x4000>;
173 interrupts = <105 106>;
176 interrupt-controller;
177 #interrupt-cells = <2>;
180 gpio7: gpio@53fe4000 {
181 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
182 reg = <0x53fe4000 0x4000>;
183 interrupts = <107 108>;
186 interrupt-controller;
187 #interrupt-cells = <2>;
191 #address-cells = <1>;
193 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
194 reg = <0x53fec000 0x4000>;
196 clocks = <&clks IMX5_CLK_I2C3_GATE>;
201 aips@60000000 { /* AIPS2 */
202 compatible = "fsl,aips-bus", "simple-bus";
203 #address-cells = <1>;
205 reg = <0x60000000 0x10000000>;
208 sdma: sdma@63fb0000 {
209 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
210 reg = <0x63fb0000 0x4000>;
212 clocks = <&clks IMX5_CLK_SDMA_GATE>,
213 <&clks IMX5_CLK_SDMA_GATE>;
214 clock-names = "ipg", "ahb";
216 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
219 fec: ethernet@63fec000 {
220 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
221 reg = <0x63fec000 0x4000>;
223 clocks = <&clks IMX5_CLK_FEC_GATE>,
224 <&clks IMX5_CLK_FEC_GATE>,
225 <&clks IMX5_CLK_FEC_GATE>;
226 clock-names = "ipg", "ahb", "ptp";
231 #address-cells = <1>;
233 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
234 reg = <0x63fc4000 0x4000>;
236 clocks = <&clks IMX5_CLK_I2C2_GATE>;
241 #address-cells = <1>;
243 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
244 reg = <0x63fc8000 0x4000>;
246 clocks = <&clks IMX5_CLK_I2C1_GATE>;