2 * Copyright 2016 Beckhoff Automation
3 * Copyright 2011 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 #include "skeleton.dtsi"
15 #include "imx53-pinfunc.h"
16 #include <dt-bindings/clock/imx5-clock.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/input/input.h>
19 #include <dt-bindings/interrupt-controller/irq.h>
42 tzic: tz-interrupt-controller@fffc000 {
43 compatible = "fsl,imx53-tzic", "fsl,tzic";
45 #interrupt-cells = <1>;
46 reg = <0x0fffc000 0x4000>;
52 compatible = "simple-bus";
53 interrupt-parent = <&tzic>;
57 aips@50000000 { /* AIPS1 */
58 compatible = "fsl,aips-bus", "simple-bus";
61 reg = <0x50000000 0x10000000>;
65 compatible = "fsl,spba-bus", "simple-bus";
68 reg = <0x50000000 0x40000>;
71 esdhc1: esdhc@50004000 {
72 compatible = "fsl,imx53-esdhc";
73 reg = <0x50004000 0x4000>;
75 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
76 <&clks IMX5_CLK_DUMMY>,
77 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
78 clock-names = "ipg", "ahb", "per";
83 esdhc2: esdhc@50008000 {
84 compatible = "fsl,imx53-esdhc";
85 reg = <0x50008000 0x4000>;
87 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
88 <&clks IMX5_CLK_DUMMY>,
89 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
90 clock-names = "ipg", "ahb", "per";
95 esdhc3: esdhc@50020000 {
96 compatible = "fsl,imx53-esdhc";
97 reg = <0x50020000 0x4000>;
99 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
100 <&clks IMX5_CLK_DUMMY>,
101 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
102 clock-names = "ipg", "ahb", "per";
107 esdhc4: esdhc@50024000 {
108 compatible = "fsl,imx53-esdhc";
109 reg = <0x50024000 0x4000>;
111 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
112 <&clks IMX5_CLK_DUMMY>,
113 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
114 clock-names = "ipg", "ahb", "per";
120 iomuxc: iomuxc@53fa8000 {
121 compatible = "fsl,imx53-iomuxc";
122 reg = <0x53fa8000 0x4000>;
125 gpr: iomuxc-gpr@53fa8000 {
126 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
127 reg = <0x53fa8000 0xc>;
130 uart2: serial@53fc0000 {
131 compatible = "fsl,imx7d-uart", "fsl,imx53-uart", "fsl,imx21-uart";
132 reg = <0x53fc0000 0x4000>;
134 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
135 <&clks IMX5_CLK_UART2_PER_GATE>;
136 clock-names = "ipg", "per";
137 dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
138 dma-names = "rx", "tx";
142 usbh1: usb@53f80200 {
143 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
144 reg = <0x53f80200 0x0200>;
146 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
152 compatible = "fsl,imx53-ccm";
153 reg = <0x53fd4000 0x4000>;
154 interrupts = <0 71 0x04 0 72 0x04>;
158 gpio1: gpio@53f84000 {
159 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
160 reg = <0x53f84000 0x4000>;
161 interrupts = <50 51>;
164 interrupt-controller;
165 #interrupt-cells = <2>;
168 gpio2: gpio@53f88000 {
169 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
170 reg = <0x53f88000 0x4000>;
171 interrupts = <52 53>;
174 interrupt-controller;
175 #interrupt-cells = <2>;
178 gpio3: gpio@53f8c000 {
179 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
180 reg = <0x53f8c000 0x4000>;
181 interrupts = <54 55>;
184 interrupt-controller;
185 #interrupt-cells = <2>;
188 gpio4: gpio@53f90000 {
189 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
190 reg = <0x53f90000 0x4000>;
191 interrupts = <56 57>;
194 interrupt-controller;
195 #interrupt-cells = <2>;
198 gpio5: gpio@53fdc000 {
199 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
200 reg = <0x53fdc000 0x4000>;
201 interrupts = <103 104>;
204 interrupt-controller;
205 #interrupt-cells = <2>;
208 gpio6: gpio@53fe0000 {
209 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
210 reg = <0x53fe0000 0x4000>;
211 interrupts = <105 106>;
214 interrupt-controller;
215 #interrupt-cells = <2>;
218 gpio7: gpio@53fe4000 {
219 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
220 reg = <0x53fe4000 0x4000>;
221 interrupts = <107 108>;
224 interrupt-controller;
225 #interrupt-cells = <2>;
229 #address-cells = <1>;
231 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
232 reg = <0x53fec000 0x4000>;
234 clocks = <&clks IMX5_CLK_I2C3_GATE>;
239 aips@60000000 { /* AIPS2 */
240 compatible = "fsl,aips-bus", "simple-bus";
241 #address-cells = <1>;
243 reg = <0x60000000 0x10000000>;
246 sdma: sdma@63fb0000 {
247 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
248 reg = <0x63fb0000 0x4000>;
250 clocks = <&clks IMX5_CLK_SDMA_GATE>,
251 <&clks IMX5_CLK_SDMA_GATE>;
252 clock-names = "ipg", "ahb";
254 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
257 fec: ethernet@63fec000 {
258 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
259 reg = <0x63fec000 0x4000>;
261 clocks = <&clks IMX5_CLK_FEC_GATE>,
262 <&clks IMX5_CLK_FEC_GATE>,
263 <&clks IMX5_CLK_FEC_GATE>;
264 clock-names = "ipg", "ahb", "ptp";
269 #address-cells = <1>;
271 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
272 reg = <0x63fc4000 0x4000>;
274 clocks = <&clks IMX5_CLK_I2C2_GATE>;
279 #address-cells = <1>;
281 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
282 reg = <0x63fc8000 0x4000>;
284 clocks = <&clks IMX5_CLK_I2C1_GATE>;
290 #address-cells = <1>;
292 compatible = "fsl,imx53-ipu";
293 reg = <0x18000000 0x08000000>;
294 interrupts = <11 10>;
295 clocks = <&clks IMX5_CLK_IPU_GATE>,
296 <&clks IMX5_CLK_IPU_DI0_GATE>,
297 <&clks IMX5_CLK_IPU_DI1_GATE>;
298 clock-names = "bus", "di0", "di1";
311 #address-cells = <1>;
315 ipu_di0_disp0: endpoint@0 {
319 ipu_di0_lvds0: endpoint@1 {
321 remote-endpoint = <&lvds0_in>;
326 #address-cells = <1>;
330 ipu_di1_disp1: endpoint@0 {
334 ipu_di1_lvds1: endpoint@1 {
336 remote-endpoint = <&lvds1_in>;
339 ipu_di1_tve: endpoint@2 {
341 remote-endpoint = <&tve_in>;
347 compatible = "fsl,imx53-tve";
348 reg = <0x63ff0000 0x1000>;
350 clocks = <&clks IMX5_CLK_TVE_GATE>,
351 <&clks IMX5_CLK_IPU_DI1_SEL>;
352 clock-names = "tve", "di_sel";
357 remote-endpoint = <&ipu_di1_tve>;
363 compatible = "fsl,imx53-src", "fsl,imx51-src";
364 reg = <0x53fd0000 0x4000>;
369 #address-cells = <1>;
371 compatible = "fsl,imx53-ldb";
372 reg = <0x53fa8008 0x4>;
374 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
375 <&clks IMX5_CLK_LDB_DI1_SEL>,
376 <&clks IMX5_CLK_IPU_DI0_SEL>,
377 <&clks IMX5_CLK_IPU_DI1_SEL>,
378 <&clks IMX5_CLK_LDB_DI0_GATE>,
379 <&clks IMX5_CLK_LDB_DI1_GATE>;
380 clock-names = "di0_pll", "di1_pll",
381 "di0_sel", "di1_sel",
386 #address-cells = <1>;
395 remote-endpoint = <&ipu_di0_lvds0>;
405 #address-cells = <1>;
414 remote-endpoint = <&ipu_di1_lvds1>;