1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2019 Marek Vasut <marex@denx.de>
7 #include "imx53-m53.dtsi"
8 #include "imx53-m53menlo-u-boot.dtsi"
11 model = "MENLO M53 EMBEDDED DEVICE";
12 compatible = "menlo,m53menlo", "fsl,imx53";
15 compatible = "gpio-leds";
16 pinctrl-names = "default";
17 pinctrl-0 = <&pinctrl_led>;
21 gpios = <&gpio6 1 GPIO_ACTIVE_HIGH>;
22 linux,default-trigger = "mmc0";
27 gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>;
28 linux,default-trigger = "heartbeat";
33 gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
34 linux,default-trigger = "none";
39 compatible = "edt,etm070080dh6";
40 enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>;
44 remote-endpoint = <&lvds0_out>;
49 reg_usbh1_vbus: regulator-usbh1-vbus {
50 compatible = "regulator-fixed";
51 regulator-name = "vbus";
52 regulator-min-microvolt = <5000000>;
53 regulator-max-microvolt = <5000000>;
54 gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
59 pinctrl-names = "default";
60 pinctrl-0 = <&pinctrl_can1>;
65 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_can2>;
71 assigned-clocks = <&clks IMX5_CLK_CKO1_SEL>,
72 <&clks IMX5_CLK_CKO1_PODF>,
73 <&clks IMX5_CLK_CKO1>;
74 assigned-clock-parents = <&clks IMX5_CLK_AHB>;
75 assigned-clock-rates = <133333334>, <33333334>, <33333334>;
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_esdhc1>;
81 cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
82 wp-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
87 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_fec>;
94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_i2c1>;
99 compatible = "edt,edt-ft5x06";
101 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_edt_ft5x06>;
103 interrupt-parent = <&gpio6>;
104 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
105 reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
106 wake-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
110 compatible = "atmel,24c64";
116 compatible = "microchip,mcp4725";
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_i2c3>;
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_hog>;
140 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4
141 MX53_PAD_EIM_EB3__GPIO2_31 0x1d5
142 MX53_PAD_PATA_DA_0__GPIO7_6 0x1d5
143 MX53_PAD_GPIO_19__CCM_CLKO 0x1d5
144 MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK 0x1d5
145 MX53_PAD_CSI0_DAT4__GPIO5_22 0x1d5
146 MX53_PAD_CSI0_DAT5__GPIO5_23 0x1d5
147 MX53_PAD_CSI0_DAT6__GPIO5_24 0x1d5
148 MX53_PAD_CSI0_DAT7__GPIO5_25 0x1d5
149 MX53_PAD_CSI0_DAT8__GPIO5_26 0x1d5
150 MX53_PAD_CSI0_DAT9__GPIO5_27 0x1d5
151 MX53_PAD_CSI0_DAT10__GPIO5_28 0x1d5
152 MX53_PAD_CSI0_DAT11__GPIO5_29 0x1d5
153 MX53_PAD_CSI0_DAT14__GPIO6_0 0x1d5
157 pinctrl_led: ledgrp {
159 MX53_PAD_CSI0_DAT15__GPIO6_1 0x1d5
160 MX53_PAD_CSI0_DAT16__GPIO6_2 0x1d5
164 pinctrl_can1: can1grp {
166 MX53_PAD_GPIO_7__CAN1_TXCAN 0x1c4
167 MX53_PAD_GPIO_8__CAN1_RXCAN 0x1c4
171 pinctrl_can2: can2grp {
173 MX53_PAD_KEY_COL4__CAN2_TXCAN 0x1c4
174 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x1c4
178 pinctrl_display_gpio: display-gpiogrp {
180 MX53_PAD_CSI0_DAT12__GPIO5_30 0x1d5 /* Reset */
181 MX53_PAD_CSI0_DAT13__GPIO5_31 0x1d5 /* Interrupt */
185 pinctrl_edt_ft5x06: edt-ft5x06grp {
187 MX53_PAD_PATA_DATA9__GPIO2_9 0x1d5 /* Reset */
188 MX53_PAD_CSI0_DAT19__GPIO6_5 0x1d5 /* Interrupt */
189 MX53_PAD_PATA_DATA10__GPIO2_10 0x1d5 /* Wake */
193 pinctrl_esdhc1: esdhc1grp {
195 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
196 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
197 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
198 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
199 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
200 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
204 pinctrl_fec: fecgrp {
206 MX53_PAD_FEC_MDC__FEC_MDC 0x4
207 MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
208 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
209 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180
210 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
211 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
212 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
213 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
214 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
215 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
219 pinctrl_i2c1: i2c1grp {
221 MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4
222 MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4
226 pinctrl_i2c3: i2c3grp {
228 MX53_PAD_GPIO_6__I2C3_SDA 0x400001e4
229 MX53_PAD_GPIO_5__I2C3_SCL 0x400001e4
233 pinctrl_lvds0: lvds0grp {
234 /* LVDS pins only have pin mux configuration */
236 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
237 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
238 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
239 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
240 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
244 pinctrl_uart1: uart1grp {
246 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
247 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
251 pinctrl_uart2: uart2grp {
253 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
254 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
258 pinctrl_usb: usbgrp {
260 MX53_PAD_GPIO_2__GPIO1_2 0x1d5
261 MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x1d5
268 pinctrl-names = "default";
269 pinctrl-0 = <&pinctrl_lvds0>;
272 lvds0: lvds-channel@0 {
274 fsl,data-mapping = "spwg";
275 fsl,data-width = <18>;
281 lvds0_out: endpoint {
282 remote-endpoint = <&panel_in>;
289 pinctrl-names = "default";
290 pinctrl-0 = <&pinctrl_uart1>;
295 pinctrl-names = "default";
296 pinctrl-0 = <&pinctrl_uart2>;
301 pinctrl-names = "default";
302 pinctrl-0 = <&pinctrl_usb>;
303 vbus-supply = <®_usbh1_vbus>;
305 dr_mode = "peripheral";
310 dr_mode = "peripheral";