arm64: zynqmp: Use only earlycon bootargs instead of full one
[oweals/u-boot.git] / arch / arm / dts / hi6220.dtsi
1 /*
2  * dts file for Hisilicon Hi6220 SoC
3  *
4  * Copyright (C) 2015, Hisilicon Ltd.
5  */
6
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/hi6220-clock.h>
9
10 / {
11         compatible = "hisilicon,hi6220";
12         interrupt-parent = <&gic>;
13         #address-cells = <2>;
14         #size-cells = <2>;
15
16         psci {
17                 compatible = "arm,psci-0.2";
18                 method = "smc";
19         };
20
21         cpus {
22                 #address-cells = <2>;
23                 #size-cells = <0>;
24
25                 cpu-map {
26                         cluster0 {
27                                 core0 {
28                                         cpu = <&cpu0>;
29                                 };
30                                 core1 {
31                                         cpu = <&cpu1>;
32                                 };
33                                 core2 {
34                                         cpu = <&cpu2>;
35                                 };
36                                 core3 {
37                                         cpu = <&cpu3>;
38                                 };
39                         };
40                         cluster1 {
41                                 core0 {
42                                         cpu = <&cpu4>;
43                                 };
44                                 core1 {
45                                         cpu = <&cpu5>;
46                                 };
47                                 core2 {
48                                         cpu = <&cpu6>;
49                                 };
50                                 core3 {
51                                         cpu = <&cpu7>;
52                                 };
53                         };
54                 };
55
56                 cpu0: cpu@0 {
57                         compatible = "arm,cortex-a53", "arm,armv8";
58                         device_type = "cpu";
59                         reg = <0x0 0x0>;
60                         enable-method = "psci";
61                 };
62
63                 cpu1: cpu@1 {
64                         compatible = "arm,cortex-a53", "arm,armv8";
65                         device_type = "cpu";
66                         reg = <0x0 0x1>;
67                         enable-method = "psci";
68                 };
69
70                 cpu2: cpu@2 {
71                         compatible = "arm,cortex-a53", "arm,armv8";
72                         device_type = "cpu";
73                         reg = <0x0 0x2>;
74                         enable-method = "psci";
75                 };
76
77                 cpu3: cpu@3 {
78                         compatible = "arm,cortex-a53", "arm,armv8";
79                         device_type = "cpu";
80                         reg = <0x0 0x3>;
81                         enable-method = "psci";
82                 };
83
84                 cpu4: cpu@100 {
85                         compatible = "arm,cortex-a53", "arm,armv8";
86                         device_type = "cpu";
87                         reg = <0x0 0x100>;
88                         enable-method = "psci";
89                 };
90
91                 cpu5: cpu@101 {
92                         compatible = "arm,cortex-a53", "arm,armv8";
93                         device_type = "cpu";
94                         reg = <0x0 0x101>;
95                         enable-method = "psci";
96                 };
97
98                 cpu6: cpu@102 {
99                         compatible = "arm,cortex-a53", "arm,armv8";
100                         device_type = "cpu";
101                         reg = <0x0 0x102>;
102                         enable-method = "psci";
103                 };
104
105                 cpu7: cpu@103 {
106                         compatible = "arm,cortex-a53", "arm,armv8";
107                         device_type = "cpu";
108                         reg = <0x0 0x103>;
109                         enable-method = "psci";
110                 };
111         };
112
113         gic: interrupt-controller@f6801000 {
114                 compatible = "arm,gic-400";
115                 reg = <0x0 0xf6801000 0 0x1000>, /* GICD */
116                       <0x0 0xf6802000 0 0x2000>, /* GICC */
117                       <0x0 0xf6804000 0 0x2000>, /* GICH */
118                       <0x0 0xf6806000 0 0x2000>; /* GICV */
119                 #address-cells = <0>;
120                 #interrupt-cells = <3>;
121                 interrupt-controller;
122                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
123         };
124
125         timer {
126                 compatible = "arm,armv8-timer";
127                 interrupt-parent = <&gic>;
128                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
129                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
130                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
131                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
132         };
133
134         soc {
135                 compatible = "simple-bus";
136                 #address-cells = <2>;
137                 #size-cells = <2>;
138                 ranges;
139
140                 ao_ctrl: ao_ctrl@f7800000 {
141                         compatible = "hisilicon,hi6220-aoctrl", "syscon";
142                         reg = <0x0 0xf7800000 0x0 0x2000>;
143                         #clock-cells = <1>;
144                 };
145
146                 sys_ctrl: sys_ctrl@f7030000 {
147                         compatible = "hisilicon,hi6220-sysctrl", "syscon";
148                         reg = <0x0 0xf7030000 0x0 0x2000>;
149                         #clock-cells = <1>;
150                         #reset-cells = <1>;
151                 };
152
153                 media_ctrl: media_ctrl@f4410000 {
154                         compatible = "hisilicon,hi6220-mediactrl", "syscon";
155                         reg = <0x0 0xf4410000 0x0 0x1000>;
156                         #clock-cells = <1>;
157                 };
158
159                 pm_ctrl: pm_ctrl@f7032000 {
160                         compatible = "hisilicon,hi6220-pmctrl", "syscon";
161                         reg = <0x0 0xf7032000 0x0 0x1000>;
162                         #clock-cells = <1>;
163                 };
164
165                 uart0: uart@f8015000 {  /* console */
166                         compatible = "arm,pl011", "arm,primecell";
167                         reg = <0x0 0xf8015000 0x0 0x1000>;
168                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
169                         clock = <19200000>;
170                         clocks = <&ao_ctrl HI6220_UART0_PCLK>,
171                                  <&ao_ctrl HI6220_UART0_PCLK>;
172                         clock-names = "uartclk", "apb_pclk";
173                 };
174
175                 uart1: uart@f7111000 {
176                         compatible = "arm,pl011", "arm,primecell";
177                         reg = <0x0 0xf7111000 0x0 0x1000>;
178                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
179                         clock = <19200000>;
180                         clocks = <&sys_ctrl HI6220_UART1_PCLK>,
181                                  <&sys_ctrl HI6220_UART1_PCLK>;
182                         clock-names = "uartclk", "apb_pclk";
183                         status = "disabled";
184                 };
185
186                 uart2: uart@f7112000 {
187                         compatible = "arm,pl011", "arm,primecell";
188                         reg = <0x0 0xf7112000 0x0 0x1000>;
189                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
190                         clock = <19200000>;
191                         clocks = <&sys_ctrl HI6220_UART2_PCLK>,
192                                  <&sys_ctrl HI6220_UART2_PCLK>;
193                         clock-names = "uartclk", "apb_pclk";
194                         status = "disabled";
195                 };
196
197                 uart3: uart@f7113000 {
198                         compatible = "arm,pl011", "arm,primecell";
199                         reg = <0x0 0xf7113000 0x0 0x1000>;
200                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
201                         clock = <19200000>;
202                         clocks = <&sys_ctrl HI6220_UART3_PCLK>,
203                                  <&sys_ctrl HI6220_UART3_PCLK>;
204                         clock-names = "uartclk", "apb_pclk";
205                 };
206
207                 uart4: uart@f7114000 {
208                         compatible = "arm,pl011", "arm,primecell";
209                         reg = <0x0 0xf7114000 0x0 0x1000>;
210                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
211                         clock = <19200000>;
212                         clocks = <&sys_ctrl HI6220_UART4_PCLK>,
213                                  <&sys_ctrl HI6220_UART4_PCLK>;
214                         clock-names = "uartclk", "apb_pclk";
215                         status = "disabled";
216                 };
217         };
218 };