1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * NXP lx2160a SOC common device tree source
10 compatible = "fsl,lx2160a";
11 interrupt-parent = <&gic>;
16 device_type = "memory";
17 reg = <0x00000000 0x80000000 0 0x80000000>;
18 /* DRAM space - 1, size : 2 GB DRAM */
22 compatible = "fixed-clock";
24 clock-frequency = <100000000>;
25 clock-output-names = "sysclk";
28 clockgen: clocking@1300000 {
29 compatible = "fsl,ls2080a-clockgen";
30 reg = <0 0x1300000 0 0xa0000>;
35 gic: interrupt-controller@6000000 {
36 compatible = "arm,gic-v3";
37 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
38 <0x0 0x06200000 0 0x100000>; /* GICR */
39 #interrupt-cells = <3>;
41 interrupts = <1 9 0x4>;
45 compatible = "arm,armv8-timer";
46 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
47 <1 14 0x8>, /* Physical NS PPI, active-low */
48 <1 11 0x8>, /* Virtual PPI, active-low */
49 <1 10 0x8>; /* Hypervisor PPI, active-low */
52 uart0: serial@21c0000 {
53 compatible = "arm,pl011";
54 reg = <0x0 0x21c0000 0x0 0x1000>;
55 clocks = <&clockgen 4 0>;
58 uart1: serial@21d0000 {
59 compatible = "arm,pl011";
60 reg = <0x0 0x21d0000 0x0 0x1000>;
61 clocks = <&clockgen 4 0>;
64 uart2: serial@21e0000 {
65 compatible = "arm,pl011";
66 reg = <0x0 0x21e0000 0x0 0x1000>;
67 clocks = <&clockgen 4 0>;
71 uart3: serial@21f0000 {
72 compatible = "arm,pl011";
73 reg = <0x0 0x21f0000 0x0 0x1000>;
74 clocks = <&clockgen 4 0>;
79 compatible = "fsl,vf610-dspi";
82 reg = <0x0 0x2100000 0x0 0x10000>;
83 interrupts = <0 26 0x4>; /* Level high type */
88 compatible = "fsl,vf610-dspi";
91 reg = <0x0 0x2110000 0x0 0x10000>;
92 interrupts = <0 26 0x4>; /* Level high type */
97 compatible = "fsl,vf610-dspi";
100 reg = <0x0 0x2120000 0x0 0x10000>;
101 interrupts = <0 241 0x4>; /* Level high type */
106 compatible = "fsl,layerscape-dwc3";
107 reg = <0x0 0x3100000 0x0 0x10000>;
108 interrupts = <0 80 0x4>; /* Level high type */
113 compatible = "fsl,layerscape-dwc3";
114 reg = <0x0 0x3110000 0x0 0x10000>;
115 interrupts = <0 81 0x4>; /* Level high type */
119 esdhc0: esdhc@2140000 {
120 compatible = "fsl,esdhc";
121 reg = <0x0 0x2140000 0x0 0x10000>;
122 interrupts = <0 28 0x4>; /* Level high type */
123 clocks = <&clockgen 4 1>;
124 voltage-ranges = <1800 1800 3300 3300>;
131 esdhc1: esdhc@2150000 {
132 compatible = "fsl,esdhc";
133 reg = <0x0 0x2150000 0x0 0x10000>;
134 interrupts = <0 63 0x4>; /* Level high type */
135 clocks = <&clockgen 4 1>;
136 voltage-ranges = <1800 1800 3300 3300>;
144 sata0: sata@3200000 {
145 compatible = "fsl,ls2080a-ahci";
146 reg = <0x0 0x3200000 0x0 0x10000>;
147 interrupts = <0 133 4>;
148 clocks = <&clockgen 4 3>;
153 sata1: sata@3210000 {
154 compatible = "fsl,ls2080a-ahci";
155 reg = <0x0 0x3210000 0x0 0x10000>;
156 interrupts = <0 136 4>;
157 clocks = <&clockgen 4 3>;
162 sata2: sata@3220000 {
163 compatible = "fsl,ls2080a-ahci";
164 reg = <0x0 0x3220000 0x0 0x10000>;
165 interrupts = <0 97 4>;
166 clocks = <&clockgen 4 3>;
171 sata3: sata@3230000 {
172 compatible = "fsl,ls2080a-ahci";
173 reg = <0x0 0x3230000 0x0 0x10000>;
174 interrupts = <0 100 4>;
175 clocks = <&clockgen 4 3>;