1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * NXP LX2160AQDS common device tree source
5 * Copyright 2018-2019 NXP
9 #include "fsl-lx2160a.dtsi"
13 phy-handle = <&rgmii_phy1>;
14 phy-connection-type = "rgmii-id";
19 phy-handle = <&rgmii_phy2>;
20 phy-connection-type = "rgmii-id";
46 compatible = "simple-mfd";
52 compatible = "mdio-mux-i2creg";
54 #mux-control-cells = <1>;
55 mux-reg-masks = <0x54 0xf8>; // reg 0x54, bits 7:3
56 mdio-parent-bus = <&emdio1>;
63 rgmii_phy1: ethernet-phy@1 {
72 rgmii_phy2: ethernet-phy@2 {
77 emdio1_slot1: mdio@c0 { /* I/O Slot #1 */
79 device-name = "emdio1_slot1";
84 emdio1_slot2: mdio@c8 { /* I/O Slot #2 */
86 device-name = "emdio1_slot2";
91 emdio1_slot3: mdio@d0 { /* I/O Slot #3 */
93 device-name = "emdio1_slot3";
98 emdio1_slot4: mdio@d8 { /* I/O Slot #4 */
100 device-name = "emdio1_slot4";
101 #address-cells = <1>;
105 emdio1_slot5: mdio@e0 { /* I/O Slot #5 */
107 device-name = "emdio1_slot5";
108 #address-cells = <1>;
112 emdio1_slot6: mdio@e8 { /* I/O Slot #6 */
114 device-name = "emdio1_slot6";
115 #address-cells = <1>;
119 emdio1_slot7: mdio@f0 { /* I/O Slot #7 */
121 device-name = "emdio1_slot7";
122 #address-cells = <1>;
126 emdio1_slot8: mdio@f8 { /* I/O Slot #8 */
128 device-name = "emdio1_slot8";
129 #address-cells = <1>;
137 compatible = "nxp,pca9547";
139 #address-cells = <1>;
143 #address-cells = <1>;
148 compatible = "pcf2127-rtc";