1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * NXP LX2160AQDS device tree source for the SERDES block #2 - protocol 11
5 * Some assumptions are made:
6 * * 2 mezzanine cards M1/M4 are connected to IO SLOT 7 and IO SLOT 8
7 * (sgmii for DPMAC 12, 13, 14, 16, 17, 18)
12 #include "fsl-lx2160a-qds.dtsi"
16 phy-handle = <&sgmii_phy7_2>;
17 phy-connection-type = "sgmii";
22 phy-handle = <&sgmii_phy7_3>;
23 phy-connection-type = "sgmii";
28 phy-handle = <&sgmii_phy7_4>;
29 phy-connection-type = "sgmii";
34 phy-handle = <&sgmii_phy8_2>;
35 phy-connection-type = "sgmii";
40 phy-handle = <&sgmii_phy8_3>;
41 phy-connection-type = "sgmii";
46 phy-handle = <&sgmii_phy8_4>;
47 phy-connection-type = "sgmii";
51 sgmii_phy7_2: ethernet-phy@1d {
55 sgmii_phy7_3: ethernet-phy@1e {
59 sgmii_phy7_4: ethernet-phy@1f {
65 sgmii_phy8_2: ethernet-phy@1d {
69 sgmii_phy8_3: ethernet-phy@1e {
73 sgmii_phy8_4: ethernet-phy@1f {