1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 7
5 * Some assumptions are made:
6 * * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4,5,6)
7 * * mezzanine card M1/M4 is connected to IO SLOT2 (sgmii for DPMAC 7,8,9,10)
12 #include "fsl-lx2160a-qds.dtsi"
16 phy-handle = <&aquantia_phy1>;
17 phy-connection-type = "usxgmii";
22 phy-handle = <&aquantia_phy2>;
23 phy-connection-type = "usxgmii";
28 phy-handle = <&aquantia_phy3>;
29 phy-connection-type = "usxgmii";
34 phy-handle = <&aquantia_phy4>;
35 phy-connection-type = "usxgmii";
40 phy-handle = <&sgmii_phy1>;
41 phy-connection-type = "sgmii";
46 phy-handle = <&sgmii_phy2>;
47 phy-connection-type = "sgmii";
52 phy-handle = <&sgmii_phy3>;
53 phy-connection-type = "sgmii";
58 phy-handle = <&sgmii_phy4>;
59 phy-connection-type = "sgmii";
63 aquantia_phy1: ethernet-phy@4 {
64 compatible = "ethernet-phy-ieee802.3-c45";
68 aquantia_phy2: ethernet-phy@5 {
69 compatible = "ethernet-phy-ieee802.3-c45";
73 aquantia_phy3: ethernet-phy@6 {
74 compatible = "ethernet-phy-ieee802.3-c45";
78 aquantia_phy4: ethernet-phy@7 {
79 compatible = "ethernet-phy-ieee802.3-c45";
85 sgmii_phy1: ethernet-phy@1c {
89 sgmii_phy2: ethernet-phy@1d {
93 sgmii_phy3: ethernet-phy@1e {
97 sgmii_phy4: ethernet-phy@1f {