1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * Freescale ls2080a SOC common device tree source
5 * Copyright 2013-2015 Freescale Semiconductor, Inc.
9 compatible = "fsl,ls2080a";
10 interrupt-parent = <&gic>;
15 device_type = "memory";
16 reg = <0x00000000 0x80000000 0 0x80000000>;
17 /* DRAM space - 1, size : 2 GB DRAM */
20 gic: interrupt-controller@6000000 {
21 compatible = "arm,gic-v3";
22 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
23 <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
24 #interrupt-cells = <3>;
26 interrupts = <1 9 0x4>;
30 compatible = "arm,armv8-timer";
31 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
32 <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
33 <1 11 0x8>, /* Virtual PPI, active-low */
34 <1 10 0x8>; /* Hypervisor PPI, active-low */
37 serial0: serial@21c0500 {
38 device_type = "serial";
39 compatible = "fsl,ns16550", "ns16550a";
40 reg = <0x0 0x21c0500 0x0 0x100>;
41 clock-frequency = <0>; /* Updated by bootloader */
42 interrupts = <0 32 0x1>; /* edge triggered */
45 serial1: serial@21c0600 {
46 device_type = "serial";
47 compatible = "fsl,ns16550", "ns16550a";
48 reg = <0x0 0x21c0600 0x0 0x100>;
49 clock-frequency = <0>; /* Updated by bootloader */
50 interrupts = <0 32 0x1>; /* edge triggered */
53 fsl_mc: fsl-mc@80c000000 {
54 compatible = "fsl,qoriq-mc";
55 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
56 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
60 compatible = "fsl,vf610-dspi";
63 reg = <0x0 0x2100000 0x0 0x10000>;
64 interrupts = <0 26 0x4>; /* Level high type */
68 qspi: quadspi@1550000 {
69 compatible = "fsl,vf610-qspi";
72 reg = <0x0 0x20c0000 0x0 0x10000>,
73 <0x0 0x20000000 0x0 0x10000000>;
74 reg-names = "QuadSPI", "QuadSPI-memory";
79 compatible = "fsl,layerscape-dwc3";
80 reg = <0x0 0x3100000 0x0 0x10000>;
81 interrupts = <0 80 0x4>; /* Level high type */
86 compatible = "fsl,layerscape-dwc3";
87 reg = <0x0 0x3110000 0x0 0x10000>;
88 interrupts = <0 81 0x4>; /* Level high type */
93 compatible = "fsl,ls-pcie", "snps,dw-pcie";
94 reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
95 0x00 0x03480000 0x0 0x80000 /* lut registers */
96 0x10 0x00000000 0x0 0x20000>; /* configuration space */
97 reg-names = "dbi", "lut", "config";
102 bus-range = <0x0 0xff>;
103 ranges = <0x81000000 0x0 0x00000000 0x10 0x00020000 0x0 0x00010000 /* downstream I/O */
104 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
108 compatible = "fsl,ls-pcie", "snps,dw-pcie";
109 reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
110 0x00 0x03580000 0x0 0x80000 /* lut registers */
111 0x12 0x00000000 0x0 0x20000>; /* configuration space */
112 reg-names = "dbi", "lut", "config";
113 #address-cells = <3>;
117 bus-range = <0x0 0xff>;
118 ranges = <0x81000000 0x0 0x00000000 0x12 0x00020000 0x0 0x00010000 /* downstream I/O */
119 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
123 compatible = "fsl,ls-pcie", "snps,dw-pcie";
124 reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
125 0x00 0x03680000 0x0 0x80000 /* lut registers */
126 0x14 0x00000000 0x0 0x20000>; /* configuration space */
127 reg-names = "dbi", "lut", "config";
128 #address-cells = <3>;
132 bus-range = <0x0 0xff>;
133 ranges = <0x81000000 0x0 0x00000000 0x14 0x00020000 0x0 0x00010000 /* downstream I/O */
134 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
138 compatible = "fsl,ls-pcie", "snps,dw-pcie";
139 reg = <0x00 0x03700000 0x0 0x80000 /* dbi registers */
140 0x00 0x03780000 0x0 0x80000 /* lut registers */
141 0x16 0x00000000 0x0 0x20000>; /* configuration space */
142 reg-names = "dbi", "lut", "config";
143 #address-cells = <3>;
147 bus-range = <0x0 0xff>;
148 ranges = <0x81000000 0x0 0x00000000 0x16 0x00020000 0x0 0x00010000 /* downstream I/O */
149 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */