1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * NXP ls1088a SOC common device tree source
9 compatible = "fsl,ls1088a";
10 interrupt-parent = <&gic>;
15 device_type = "memory";
16 reg = <0x00000000 0x80000000 0 0x80000000>;
17 /* DRAM space - 1, size : 2 GB DRAM */
20 gic: interrupt-controller@6000000 {
21 compatible = "arm,gic-v3";
22 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
23 <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
24 #interrupt-cells = <3>;
26 interrupts = <1 9 0x4>;
30 compatible = "arm,armv8-timer";
31 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
32 <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
33 <1 11 0x8>, /* Virtual PPI, active-low */
34 <1 10 0x8>; /* Hypervisor PPI, active-low */
38 compatible = "fsl,vf610-i2c";
41 reg = <0x0 0x2000000 0x0 0x10000>;
42 interrupts = <0 34 4>;
46 compatible = "fsl,vf610-i2c";
49 reg = <0x0 0x2010000 0x0 0x10000>;
50 interrupts = <0 34 4>;
54 compatible = "fsl,vf610-i2c";
57 reg = <0x0 0x2020000 0x0 0x10000>;
58 interrupts = <0 35 4>;
62 compatible = "fsl,vf610-i2c";
65 reg = <0x0 0x2030000 0x0 0x10000>;
66 interrupts = <0 35 4>;
69 serial0: serial@21c0500 {
70 device_type = "serial";
71 compatible = "fsl,ns16550", "ns16550a";
72 reg = <0x0 0x21c0500 0x0 0x100>;
73 clock-frequency = <0>; /* Updated by bootloader */
74 interrupts = <0 32 0x1>; /* edge triggered */
77 serial1: serial@21c0600 {
78 device_type = "serial";
79 compatible = "fsl,ns16550", "ns16550a";
80 reg = <0x0 0x21c0600 0x0 0x100>;
81 clock-frequency = <0>; /* Updated by bootloader */
82 interrupts = <0 32 0x1>; /* edge triggered */
86 compatible = "fsl,vf610-dspi";
89 reg = <0x0 0x2100000 0x0 0x10000>;
90 interrupts = <0 26 0x4>; /* Level high type */
94 qspi: quadspi@1550000 {
95 compatible = "fsl,ls1088a-qspi";
98 reg = <0x0 0x20c0000 0x0 0x10000>,
99 <0x0 0x20000000 0x0 0x10000000>;
100 reg-names = "QuadSPI", "QuadSPI-memory";
104 esdhc: esdhc@2140000 {
105 compatible = "fsl,esdhc";
106 reg = <0x0 0x2140000 0x0 0x10000>;
107 interrupts = <0 28 0x4>; /* Level high type */
113 compatible = "fsl,ifc", "simple-bus";
114 reg = <0x0 0x2240000 0x0 0x20000>;
115 interrupts = <0 21 0x4>; /* Level high type */
119 compatible = "fsl,layerscape-dwc3";
120 reg = <0x0 0x3100000 0x0 0x10000>;
121 interrupts = <0 80 0x4>; /* Level high type */
126 compatible = "fsl,layerscape-dwc3";
127 reg = <0x0 0x3110000 0x0 0x10000>;
128 interrupts = <0 81 0x4>; /* Level high type */
133 compatible = "fsl,ls-pcie", "snps,dw-pcie";
134 reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
135 0x00 0x03480000 0x0 0x80000 /* lut registers */
136 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
137 0x20 0x00000000 0x0 0x20000>; /* configuration space */
138 reg-names = "dbi", "lut", "ctrl", "config";
139 #address-cells = <3>;
143 bus-range = <0x0 0xff>;
144 ranges = <0x81000000 0x0 0x00000000 0x20 0x00020000 0x0 0x00010000 /* downstream I/O */
145 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
149 compatible = "fsl,ls-pcie", "snps,dw-pcie";
150 reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
151 0x00 0x03580000 0x0 0x80000 /* lut registers */
152 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
153 0x28 0x00000000 0x0 0x20000>; /* configuration space */
154 reg-names = "dbi", "lut", "ctrl", "config";
155 #address-cells = <3>;
159 bus-range = <0x0 0xff>;
160 ranges = <0x81000000 0x0 0x00000000 0x28 0x00020000 0x0 0x00010000 /* downstream I/O */
161 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
165 compatible = "fsl,ls-pcie", "snps,dw-pcie";
166 reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
167 0x00 0x03680000 0x0 0x80000 /* lut registers */
168 0x00 0x036c0000 0x0 0x40000 /* pf controls registers */
169 0x30 0x00000000 0x0 0x20000>; /* configuration space */
170 reg-names = "dbi", "lut", "ctrl", "config";
171 #address-cells = <3>;
175 bus-range = <0x0 0xff>;
176 ranges = <0x81000000 0x0 0x00000000 0x30 0x00020000 0x0 0x00010000 /* downstream I/O */
177 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
181 compatible = "fsl,ls1088a-ahci";
182 reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
183 0x7 0x100520 0x0 0x4>; /* ecc sata addr*/
184 reg-names = "sata-base", "ecc-addr";
185 interrupts = <0 133 4>;
190 compatible = "arm,psci-0.2";
194 fsl_mc: fsl-mc@80c000000 {
195 compatible = "fsl,qoriq-mc", "simple-mfd";
196 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
197 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
198 #address-cells = <3>;
202 * Region type 0x0 - MC portals
203 * Region type 0x1 - QBMAN portals
205 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
206 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
209 compatible = "simple-mfd";
210 #address-cells = <1>;
214 compatible = "fsl,qoriq-mc-dpmac";
220 compatible = "fsl,qoriq-mc-dpmac";
226 compatible = "fsl,qoriq-mc-dpmac";
232 compatible = "fsl,qoriq-mc-dpmac";
238 compatible = "fsl,qoriq-mc-dpmac";
244 compatible = "fsl,qoriq-mc-dpmac";
250 compatible = "fsl,qoriq-mc-dpmac";
256 compatible = "fsl,qoriq-mc-dpmac";
262 compatible = "fsl,qoriq-mc-dpmac";
268 compatible = "fsl,qoriq-mc-dpmac";
275 emdio1: mdio@8B96000 {
276 compatible = "fsl,ls-mdio";
277 reg = <0x0 0x8B96000 0x0 0x1000>;
278 #address-cells = <1>;
283 emdio2: mdio@8B97000 {
284 compatible = "fsl,ls-mdio";
285 reg = <0x0 0x8B97000 0x0 0x1000>;
286 #address-cells = <1>;